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2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM
PRELIMINARY IDT72T6480
FEATURES
* Product to be used with single or multiple external DDR SDRAM
to provide significant storage capability of up to 1Gb density
* IDT Standard mode or FWFT mode of operation * Empty and full flags for monitoring memory status * Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets or serially programmed to a specific value * Selectable synchronous/asynchronous timing modes for Almost-Empty and Almost-Full flags * Master Reset clears all data and settings * Partial Reset clears data, but retains programmable settings * Depth expandable with multiple devices for densities greater than 1Gb * Width expandable with multiple devices for bus widths greater than 36 bits * JTAG functionality (Boundary Scan) * Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm * HIGH performance 0.18m CMOS technology * Industrial temperature range (-40C to +85C) is available * Supports industry standard DDR specifications, including Samsung, Micron, and Infineon memories
* 133MHz operation (7.5ns read/write cycle time) * User selectable input and output port bus-sizing
- x48in to x48out - x48in to x24out - x48in to x12out - x24in to x48out - x24in to x24out - x24in to x12out - x12in to x48out - x12in to x24out - x12in to x12out For other bus configurations see IDT72T6360 (x9, x18, or x36) 2.5V-LVTTL or 3.3V-LVTTL configured ports Independent and simultaneous read and write access User selectable synchronous/asynchronous read and write port timing
* * * *
FUNCTIONAL BLOCK DIAGRAM
FWFT
I/O Bus Configuration
36-bits
FF/IR PAF EF/OR PAE
Flag Logic
Reset Logic
FSEL[1:0]
IDT72T6480 Sequential Flow Control Device
MRS PRS
IOSEL BM[3:0]
36-bits
x48, x24, or x12
Output Register
Input Register
x48, x24, or x12
36-bits
WEN WCLK/WR WCS ASYW
Read Control Logic
Write Control Logic
REN RCLK/RD RCS ASYR
DDR SDRAM Control Logic
CK MCLK CK DQS WE CAS RAS Addr
Data
JTAG Control (Boundary Scan)
TDO/SO TCK/SCLK TMS TDI/SI
8
13
64
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High Density DDR SDRAM x16, x32, x36, or x64 128Mb to 256Mb
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
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2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
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Table of Contents
Features ......................................................................................................................................................................................................................... 1 Description ...................................................................................................................................................................................................................... 4 Pin Configuration ............................................................................................................................................................................................................. 6 Pin Descriptions .......................................................................................................................................................................................................... 7-10 - Read Port Interface ........................................................................................................................................................................................... 7 - Write Port Interface ............................................................................................................................................................................................ 7 - Memory Interface .............................................................................................................................................................................................. 8 - Control and Feature Interface ............................................................................................................................................................................ 8 - Power and Ground Signals ............................................................................................................................................................................. 10 - Pin Number Location Table .............................................................................................................................................................................. 10 Detailed Descriptions ..................................................................................................................................................................................................... 11 Functional Descriptions .................................................................................................................................................................................................. 22 Signal Descriptions ........................................................................................................................................................................................................ 23 Device Characteristics ................................................................................................................................................................................................... 27 AC Test Conditions ........................................................................................................................................................................................................ 29 AC Electrical Characteristics ........................................................................................................................................................................................... 30 JTAG Timing Specifications ............................................................................................................................................................................................ 45 Depth Expansion Configuration ..................................................................................................................................................................................... 49 Width Expansion Configuration ...................................................................................................................................................................................... 50 Ordering Information ...................................................................................................................................................................................................... 51
List of Tables
Table 1 - DDR SDRAM Minimum Specifications ............................................................................................................................................................. 11 Table 2 - Supported Memory Vendors .......................................................................................................................................................................... 11 Table 3 - Total Possible External Memory Configurations ............................................................................................................................................... 12 Table 4 - SFC to DDR SDRAM interface Connections ................................................................................................................................................... 14 Table 5 - Total useable memory based on various configurations ................................................................................................................................... 18 Table 6 - IDT72T6480 Maximum Frequency Based on 166MHz DDR SDRAM ............................................................................................................ 19 Table 7 - IDT72T6480 Maximum Frequency Based on 133MHz DDR SDRAM ............................................................................................................ 19 Table 8 - MIC[2:0] Configurations .................................................................................................................................................................................. 20 Table 9 - Memory Configurations Settings ..................................................................................................................................................................... 21 Table 10 - Device configuration ..................................................................................................................................................................................... 22 Table 11- Default Programmable Flag Offsets ................................................................................................................................................................. 22 Table 12- Number of Bits Required for Offset Registers .................................................................................................................................................. 22 Table 13 - Bus-Matchings ............................................................................................................................................................................................. 24 Table 14 - MTYPE[1:0] Configurations .......................................................................................................................................................................... 25 Table 15 - Parameters affected by I/O selection ............................................................................................................................................................. 25
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List of Figures
Figure 1. Sequential Flow-Control Device Block Diagram ................................................................................................................................................ 5 Figure 2a. Configuration 1 - Two Chip Solution .............................................................................................................................................................. 13 Figure 2b. Configuration 2 - Two Chip Solution .............................................................................................................................................................. 13 Figure 2c. Configuration 3 - Three Chip Solution ........................................................................................................................................................... 13 Figure 2d. Configuration 4 - Three Chip Solution ........................................................................................................................................................... 13 Figure 2e. Configuration 5 - Three Chip Solution ........................................................................................................................................................... 13 Figure 2f. Configuration 6 - Four Chip Solution .............................................................................................................................................................. 13 Figure 2g. Configuration 7 - Five Chip Solution .............................................................................................................................................................. 13 Figure 3. Memory Interface Connection (Single Chip) .................................................................................................................................................... 17 Figure 4. Memory Interface Connection (Two Chip) ....................................................................................................................................................... 17 Figure 5a. AC Test Load ................................................................................................................................................................................................ 29 Figure 5b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 29 Figure 6. Master Reset and Initialization ......................................................................................................................................................................... 32 Figure 7. Partial Reset ................................................................................................................................................................................................... 33 Figure 8. Write First Word Cycles - IDT Standard Mode ................................................................................................................................................. 34 Figure 9. Write First Word Cycles - FWFT Mode ............................................................................................................................................................ 34 Figure 10. Empty Boundary - IDT Standard Mode ........................................................................................................................................................ 35 Figure 11. Empty Boundary - FWFT Mode .................................................................................................................................................................... 35 Figure 12. Full Boundary - IDT Standard Mode ............................................................................................................................................................ 36 Figure 13. Full Boundary - FWFT Mode ....................................................................................................................................................................... 36 Figure 14. Output Enable ............................................................................................................................................................................................... 37 Figure 15. Read Chip Select ......................................................................................................................................................................................... 37 Figure 16. Write Chip Select .......................................................................................................................................................................................... 37 Figure 17. Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode .......................................................................................................... 38 Figure 18. Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode .......................................................................................................... 38 Figure 19. Bus-Matching Configuration - x24 In to x48 Out - IDT Standard Mode .......................................................................................................... 39 Figure 20. Bus-Matching Configuration - x12 In to x48 Out - IDT Standard Mode .......................................................................................................... 39 Figure 21. Synchronous PAE Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40 Figure 22. Synchronous PAF Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40 Figure 23. Asynchronous Read and PAF Flag - IDT Standard Mode ............................................................................................................................. 41 Figure 24. Asynchronous Write and PAE Flag - IDT Standard Mode .............................................................................................................................. 41 Figure 25. Asynchronous Write and PAF Flag - IDT Standard Mode .............................................................................................................................. 41 Figure 26. Asynchronous Empty Boundary - IDT Standard Mode .................................................................................................................................. 42 Figure 27. Asynchronous Full Boundary - IDT Standard Mode...................................................................................................................................... 42 Figure 28. Asynchronous Read and PAE Flag - IDT Standard Mode ............................................................................................................................ 42 Figure 29. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) ...................................................................................... 43 Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes) ............................................................................................... 43 Figure 31. Standard JTAG Timing ................................................................................................................................................................................. 44 Figure 32. JTAG Architecture ......................................................................................................................................................................................... 45 Figure 33. TAP Controller State Diagram ....................................................................................................................................................................... 46 Figure 34. Depth Expansion Configuration in IDT Standard Mode ................................................................................................................................. 49 Figure 35. Depth Expansion Configuration in FWFT Mode ............................................................................................................................................ 49 Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode ....................................................................................................... 50
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DESCRIPTION
The IDT72T6480 sequential flow-control device is a device incorporating a seamless connection to external DDR SDRAM for significant storage capacity supporting high-speed applications. Both read and write ports of the sequential flow-control can operate independently at up to 133MHz. There is a user selectable correction feature that will correct any erroneous single data bit when reading from the SDRAM. The independent read and write ports each has associated read and write clocks, enables, and chip selects. Both ports can operate either synchronously or asynchronously. Other features include bus-matching, programmable status flags with selectable synchronous/asynchronous timing modes, IDT Standard or FWFT mode timing, and JTAG boundary scan functionality. The bus-matching feature will allow the inputs and outputs to be configured to x48, x24, or x12 bus width. There are four default offset values available
for the programmable flags (PAE/PAF), as well as the option of serially programming the offsets to a specific value. The device package is 19mm x 19mm 324-pin PBGA. It operates at a 2.5V core voltage with selectable 2.5V or 3.3V I/Os. The I/O interface to the SDRAM will be 2.5V SSTL_2 only and not 3.3V tolerant. Both industrial and commercial temperature ranges will be offered. The sequential flow-control device controls individual DDR SDRAM of either 128Mb or 256Mb. The device will support industry standard DDR specification memories (note DDR II is not supported), which include vendors such as Samsung, Micron, and Infineon. The data bus connected to the DDR SDRAM can be 16-bit, 32-bit, or 64-bits wide. The sequential flow-control device can independently control up to four separate external memories for a maximum of density of 1Gb (128MB). Depth expansion mode is available for applications that require more than 1Gb of storage memory.
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D[47:0]
48
Input Register
Output Register
48
Q[47:0]
48
48
Input Bus-Matching Logic
Output Bus-Matching Logic
QP Cache Control Logic
Refresh Counter
144 144
144
144
QP Cache 72 x 36
QP Cache 72 x 36
Multi-Clock Arbitration Circuits
State Machine Memory Interface
72
optional 72 bypass
72
optional 72 bypass
Error 72 Detection Correction
Check Bit Generator
Error 72 72 Detection Correction
Check Bit Generator
72
Logic Control Circuits
DQS[7:0] DQ[63:0] ADDR[12:0]
optional bypass 72
Memory 13 Interface BA[1:0] Address and WE Control
CAS RAS CK CK
72
optional bypass 72
72
Memory Interface Data and Bus-Matching
DLL
PLL
MCLK
64 DQ[63:0]
8 DQS[7:0]
TMS TDI TCK JTAG TDO
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Figure 1. Sequential Flow-Control Device Block Diagram
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PIN CONFIGURATION
A1 BALL PAD CORNER
A
GND GND DQ10 DQ8 DQ4 DQ1 CK A1 A5 A9 WE RAS DQ35 DQ36 DQ38 DQ40 GND GND
B
GND GND DQS1 DQ9 DQ5 DQ2 AVCC A0 A4 A10 BA1 DQ32 DQS4 DQ39 DQ44 DQS5 GND GND
C
DQ14 DQ13 DQ11 DQ12 DQ6 DQ3 CK A2 A6 A11 BA0 DQ34 DQ37 DQ41 DQ47 DQ45 DQ49 DQ50
D
DQ16 DQ15 DQ17 DQ7 DQS0 DQ0 AVCC A3 A7 A8 A12 CAS DQ33 DQ43 DQ46 VREF DQ51 DQS6
E
DQ19 DQ18 DQS2 DQ20 DQ21 AGND AGND VCC VCC VCC VCC VCC VCC DQ42
F
DQ23 DQ22 DQ24 DQ25 DQ26 VCC VCC VCC VCC VCC VCC VCC VCC DQ59
G
DQS3 DQ27 DQ28 DQ29 DQ30 VCC VCC GND GND GND
GND
H
MCLK DQ31 D0 D1 D2 VCC GND GND GND GND
GND
J
D4 D3 D5 D6 D7 VCC
GND
K
D11 D12 D10 D9 D8 VCC
GND
L
D16 D17 D15 D14
M
D21 D22 D20 D19
N
D26 D27
D25
P
D31 D32
D30
P
D24 D29 D38 D40 D43 D47
E R
D13 VCC VCC D18 VCC VCC D23 VCC VCC D28 FSEL1 D45 FSEL0 D41 ASYW D46 PRS MRS ASYR WEN
IM L
GND GND GND GND GND GND GND GND GND VCC GND GND VCC VCC VCC VCC BM3 MIC0 BM2 MIC1 BM1 TMS MIC2 WCLK/ WR RCLK/ RD REN
GND
A IN
VCC VCC VCC GND VDDQ VDDQ GND VDDQ VDDQ GND VDDQ VDDQ GND VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ Q23 TDO/SO Q47 Q32 FF/ IR PAF Q46 Q42 Q45 Q41
Y R
DQ54 DQ48 DQ52 DQ58 DQ55 DQ56 DQ62 DQ61 DQS7 Q2 Q1 DQ63 Q6 Q5 Q3 Q7 Q12 Q8 Q13 Q11 Q10 Q28 Q15 Q16 Q29 Q19 Q20 Q33 Q31 Q25
DQ53
DQ57
DQ60
Q0
Q4
GND
Q9
GND
Q14
GND
Q17
VCC
Q18
IOSEL
JSEL
Q21
R
D34 D35 D33 IDEM MTYPE0 TDI/SI Q34 Q30 Q26 Q22
T
D36 D37 D39 WCS MSPEED SWEN Q35 Q36 Q27 Q24
U
GND GND D42 FWFT MTYPE1 BM0 TCK/ SCLK SREN OE PAE Q43 Q39 Q37 GND GND
V
GND GND D44 RCS
EF/ OR
Q44
Q40
Q38
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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PBGA (BB324-1, order code: BB) TOP VIEW
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PIN DESCRIPTIONS
Symbol Pin No. Location V6 Name I/O TYPE Description
READ PORT INTERFACE ASYR(1) Asynchronous Read Port Empty Flag/ Output Ready Output Enable INPUT A HIGH on this input during master reset will select synchronous read operation for the 3.3V or output port. A LOW will select asynchronous operation. If asynchronous is selected the 2.5V LVTTL device must operate in IDT Standard mode and the read enable must be tied to GND. OUTPUT In IDT Standard mode, the EF function is selected. EF indicates whether or not the device 3.3V or memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not 2.5V LVTTL there is valid data available at the outputs. INPUT Asynchronous three-state control of the data outputs. All data outputs Q[47:0] will be placed 3.3V or in high-impedance if this pin is HIGH. Conversely, all data outputs will be active when this 2.5V LVTTL pin is LOW. OUTPUT This is the programmable almost empty flag that can be used as an early indicator for the 3.3V or empty boundary condition of the internal memory. PAE goes LOW if the number of words 2.5V LVTTL in the sequential flow-control device is less than offset n, which is stored in the empty offset register. PAE goes HIGH if the number of words in the sequential flow-control device is greater than or equal to the offset n. OUTPUT Data outputs for a 48, 24, and 12-bit bus. 3.3V or 2.5V LVTTL INPUT This is a dual function pin. If synchronous operation of the read port is selected, the rising 3.3V or edge of RCLK reads data from the sequential flow-control device when REN is enabled. 2.5V LVTTL If asynchronous operation of the read port is selected, a rising edge on RD reads data from the sequential flow-control device without the need of a free-running input read clock. INPUT Synchronous three-state control of the data outputs. Provides another means of controlling 3.3V or the data outputs synchronous to RCLK. Can be regarded as a second output enable signal. 2.5V LVTTL INPUT REN enables RCLK for reading data from the sequential flow-control device. If 3.3V asynchronous mode is selected on the read port, this signal should be tied to GND. 2.5V LVTTL INPUT When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and 3.3V or PAF offset registers are copied to a serial shift register. While SREN is maintained LOW, on 2.5V LVTTL each rising edge of SCLK, one bit of data is shifted out of this serial shift register through the SO output pin used only when JSEL = 0. INPUT 3.3V or 2.5V LVTTL INPUT 3.3V or 2.5V LVTTL A HIGH on this input during master reset will select synchronous write operation for the input port. A LOW will select asynchronous operation. If asynchronous is selected the device must operate in IDT Standard mode and the write enable must be tied to GND. Data inputs for a 48, 24, and 12-bit bus.
EF/OR
V13
OE
U12
PAE
U13
Programmable Almost Empty Flag
Q[47:0]
See Pin No. table V9
Data Output Bus
RCLK/ RD
Read Clock/ Read Strobe
RCS
V12
Read Chip Select
REN
V10
Read Enable
SREN
V11
Serial Read Enable
WRITE PORT INTERFACE T6 Asynchronous ASYW(1) Write Port D[47:0] See Pin No. table R12 Data Inputs
FF/IR
Full Flag/ Input Ready Programmable Almost Full Flag
OUTPUT In IDT Standard mode, the FF function is selected. FF indicates whether or not the device 3.3V or memory is full. In FWFT mode, the IR function is selected. IR indicates whether or not there 2.5V LVTTL is space available for writing to the device memory. OUTPUT This is the programmable almost full flag that can be used as an early indicator for the full 3.3V or boundary condition of the internal memory. PAF goes HIGH if the number of free locations 2.5V LVTTL in the sequential flow-control device is more than offset m, which is stored in the full offset register. PAF goes LOW if the number of free locations in the sequential flow-control device is less than or equal to the offset m. INPUT On each rising edge of SCLK when SWEN is LOW, data from the SI pin is serially loaded 3.3V or into the PAE and PAF registers used only when JSEL = 0. 2.5V LVTTL
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PAF
T12
SWEN
T11
Serial Write Enable
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
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PIN DESCRIPTIONS (Continued)
Symbol Pin No. Location Name I/O TYPE Description
WRITE PORT INTERFACE (Continued) WCLK/WR V8 Write Clock/ Write Strobe
INPUT This is a dual function pin. If synchronous operation of the write port is selected, the rising 3.3V or edge of WCLK writes data into the sequential flow-control device when WEN is enabled. 2.5V LVTTL If asynchronous operation of the write port is selected, a rising edge on WR writes data into the sequential flow-control device without the need of a free-running input write clock. INPUT Synchronous three-state control of the data inputs. Provides a means of controlling the 3.3V or data inputs synchronous to WCLK. Typically used to avoid bus-contention when multiple 2.5V LVTTL devices are sharing the same input data bus. INPUT WEN enables WCLK for writing data into the sequential flow-control device. If 3.3V or asynchronous mode is selected on the write port, this signal should be tied to GND. 2.5V LVTTL OUTPUT SSTL_2 OUTPUT SSTL_2 OUTPUT SSTL_2 OUTPUT SSTL_2 OUTPUT SSTL_2 Output address bus to be connected to the input address bus of the external memory to provide row and column address. Address bits to be connected to the external memory's BA inputs to determine which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Clock output to be connected to the external memory's input clock. Differential clock output to be connected to the external memory's differential input clock. Output enable signal to be connected to the external memory's CAS pin to activate and deactivate the column address strobe.
WCS
T7
Write Chip Select
WEN
V7
Write Enable
MEMORY INTERFACE A[12:0] See Pin Memory Address No. table Bus BA[1:0] CK CK CAS DQ[63:0] DQS[7:0] RAS WE BA1-B11 BA0-C11 C7 A7 D12 See Pin No. table See Pin No. table A12 A11 Memory Bank Address Input Bit Memory Clock Memory Clock Inverted Memory Column Address Strobe Memory Data Bus Memory Data Strobe Memory Row Address Strobe Memory Write Enable
Bi-Directional Input/output data bus for the external memory's data bus. SSTL_2 Bi-Directional Input/output data strobe to be connected to the external memory's data strobe. SSTL_2 OUTPUT SSTL_2 OUTPUT SSTL_2 Output strobe signal to be connected to the external memory's RAS pin to activate and deactivate the row address strobe. Output strobe signal to be connected to the external memory's WE pin to activate and deactivate the write address strobe.
CONTROL AND FEATURE INTERFACE BM[3:0](1) See Pin Bus-Matching Bit No. table
FSEL[1:0](1) FSEL1-P6 Flag Select Bit
INPUT Selects the bus width of the read and write ports. 3.3V or 2.5V LVTTL INPUT During master reset, these inputs will select one of four default values for the programmable 3.3V or flags PAE and PAF. The selected value will apply to both PAE and PAF offset. 2.5V LVTTL INPUT During master reset, a HIGH on this input selects FWFT timing mode. A LOW selects IDT 3.3V or Standard timing mode. 2.5V LVTTL
FSEL0-R6 FWFT(1) U7 First Word Fall Through
IDEM(1)
R7
IDT Standard Mode INPUT This select pin is used for depth expansion configuration in IDT Standard mode. If this pin Depth Expansion 3.3V or is tied HIGH, then the FF/IR signal will be inverted to provide a seamless depth Mode Select 2.5V LVTTL expansion interface. If depth expansion in FWFT mode is desired, this pin should be tied to GND. If no depth expansion is used, this pin should be tied to GND. I/O VDDQ Select INPUT This input determines whether the inputs and outputs will tolerate a 2.5V or 3.3V voltage 3.3V or signals. If IOSEL is HIGH, then all I/Os will be 2.5V tolerant. If IOSEL is LOW, then all I/Os 2.5V LVTTL will be 3.3V tolerant. See table 15, for a list of affected I/O signals.
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IOSEL(1)
P7
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
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PIN DESCRIPTIONS (Continued)
Symbol Pin No. Location Name I/O TYPE Description
CONTROL AND FEATURE INTERFACE (Continued) JSEL(1) P11 JTAG Select INPUT This pin selects whether the JTAG pins will be used for serial programming. If JSEL is 3.3V or HIGH, the JTAG pins will only be used for JTAG boundary-scan function. If JSEL is LOW, 2.5V LVTTL the JTAG function is disabled and the JTAG pins will be used for serial programming of the PAE/PAF offset registers. MIC[2:0](1) MIC2-U10 Memory MIC1-R10 Configuration MIC0-P10 MCLK H1 Master Clock INPUT These signals enable the EDC feature of the device. See Table 8, MIC[2:0] Configurations 3.3V or for details. 2.5V LVTTL INPUT 33MHz reference clock used to generate CK and CK for external memory interface. 3.3V or 2.5V LVTTL INPUT Master reset initializes the read and write pointers to zero and sets the output register to all 3.3V or zeros. All initialized settings for the device will be configured during master reset. 2.5V LVTTL INPUT This input select the speed of the external memory interfacing the sequential flow-control 3.3V or device. A LOW selects 133MHz, and HIGH selects 166MHz. 2.5V LVTTL INPUT These inputs select which type of external memory is interfacing the sequential flow-control 3.3V or device. See Table 14 for the list of selectable memories. 2.5V LVTTL INPUT Partial reset initializes the read and write pointers to zero and sets the output registers to all 3.3V or zeros. All existing configurations in the sequential flow-control device will not be affected. 2.5V LVTTL This includes the IDT Standard or FWFT mode timing, programmable flag settings, and bus width and data rate mode. INPUT This is a dual function pin. When the JSEL pin is HIGH, this is the clock input for JTAG boundary3.3V or scan function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations 2.5V LVTTL of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. When the JSEL pin is LOW, this is the serial clock input for writing and reading the PAE/PAF offset registers. On the rising edge of every SCLK when SWEN is LOW, one bit of data from the SI pin is shifted into the PAE and PAF offset registers. On the rising edge of each SCLK when SREN is LOW, one bit of data from the SO pin is shifted out of the PAE and PAF offset registers. If the JTAG or serial programming is not used this signal needs to be tied to GND. INPUT This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data input pin. One 3.3V or of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan 2.5V LVTTL operation, test data serially loaded via the TDI on the rising edge of TCK to the Instruction Register, ID Register and Bypass Register. When the JSEL pin is LOW, this is the serial input pin for the PAE/PAF offset registers. An internal pull-up resistor forces TDI/SI HIGH if left unconnected. OUTPUT This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data output pin. 3.3V or One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary 2.5V LVTTL scan operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high-impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. When the JSEL pin is LOW, this is the serial data output pin for the PAE/PAF offset registers. INPUT TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS 3.3V or directs the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH 2.5V LVTTL if left unconnected.
MRS
V5
Master Reset
MSPEED(1)
T8
Memory Speed
MTYPE(1) MTYPE1-U8 Memory Type [1:0] MTYPE0-R8 [1:0] PRS U6 Partial Reset
TCK/ SCLK
U11
JTAG Clock/ Serial Clock
TDI/SI
R11
JTAG Test Data Input/ Serial Input
TDO/SO
P12
JTAG Test Data Output/Serial Output
TMS
T10
JTAG Mode Select
NOTE: 1. These pins should not change after master reset.
Please see next page for Power & Ground pins and Pin Number Location Table.
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PIN DESCRIPTIONS (Continued)
Pin No. Name Location POWER AND GROUND SIGNALS VCC See Pin Core VCC and No. table Output voltage for DDR SDRAM AVCC VDDQ VREF GND AGND B7, D7 See Pin No. table D16 E6, E7 Internal PLL VCC Output rail voltage for I/Os Reference Voltage Ground pin for analog circuit Symbol I/O TYPE Description
Power
The core power supply pins for the device as well as to the external DDR SDRAM. Needs to be connected to a +2.5V VCC power plane. The power supply pins for the internal PLL of the device. Needs to be connected to a +2.5V supply rail. This pin is used to provide power to the output drivers. The nominal values are 2.5V or 3.3V, depending on the state of the IOSEL pin. This is a voltage reference input to the SDRAM and must be connected to VCC/2. The ground pins for the device that must be connected to the ground plane. The ground pins for the analog circuitry in the device that must be connected to the ground plane.
Power Power Power Ground Ground
See Pin table Ground Pin
PIN NUMBER LOCATION TABLE
Symbol A[12:0] BM[3:0] Name Memory Address Bus Bus-Matching I/O TYPE OUTPUT SSTL_2 Pin Number A12-D11, A11-C10, A10-B10, A9-A10, A8-D10, A7-D9, A6-C9, A5-A9, A4-B9, A3-D8, A2-C8, A1-A8, A0-B8
INPUT BM3-P9, BM2-R9, BM1-T9, BM0-U9 3.3V or 2.5V LVTTL INPUT D47-V4, D46-U5, D45-R5, D44-V3, D43-U4, D42-U3, D41-T5, D40-T4, D39-T3, D38-R4, D37-T2, 3.3V or D36-T1, D35-R2, D34-R1, D33-R3, D32-P2, D31-P1, D30-P3, D29-P4, D28-P5, D27-N2, D26-N1, 2.5V LVTTL D25-N3, D24-N4, D23-N5, D22-M2, D21-M1, D20-M3, D19-M4, D18-M5, D17-L2, D16-L1, D15-L3, D14-L4, D13-L5, D12-K2, D11-K1, D10-K3, D9-K4, D8-K5, D7-J5, D6-J4, D5-J3, D4-J1, D3-J2, D2-H5, D1-H4, D0-H3 Bi-Directional DQ63-H17, DQ62-G15, DQ61-G16, DQ60-G18, DQ59-F14, DQ58-F15, DQ57-F18, DQ56-F17, SSTL_2 DQ55-F16, DQ54-E15, DQ53-E18, DQ52-E17, DQ51-D17, DQ50-C18, DQ49-C17, DQ48-E16, DQ47-C15, DQ46-D15, DQ45-C16, DQ44-B15, DQ43-D14, DQ42-E14, DQ41-C14, DQ40-A16, DQ39-B14, DQ38-A15, DQ37-C13, DQ36-A14, DQ35-A13, DQ34-C12, DQ33-D13, DQ32-B12, DQ31-H2, DQ30-G5, DQ29-G4, DQ28-G3, DQ27-G2, DQ26-F5, DQ25-F4, DQ24-F3, DQ23-F1, DQ22-F2, DQ21-E5, DQ20-E4, DQ19-E1, DQ18-E2, DQ17-D3, DQ16-D1, DQ15-D2, DQ14-C1, DQ13-C2, DQ12-C4, DQ11-C3, DQ10-A3, DQ9-B4, DQ8-A4, DQ7-D4, DQ6-C5, DQ5-B5, DQ4-A5, DQ3-C6, DQ2-B6, DQ1-A6, DQ0-D6, Bi-Directional DQS7-G17, DQS6-D18, DQS5-B16, DQS4-B13, DQS3-G1, DQS2-E3, DQS1-B3, DQS0-D5 SSTL_2 Output Q47-P13, Q46-R13, Q45-T13, Q44-V14, Q43-U14, Q42-R14, Q41-T14, Q40-V15, Q39-U15, Q38-V16, 3.3V or Q37-U16, Q36-T16, Q35-T15, Q34-R15, Q33-P15, Q32-P14, Q31-P16, Q30-R16, Q29-N15, Q28-M15, 2.5V LVTTL Q27-T17, Q26-R17, Q25-P17, Q24-T18, Q23-N14, Q22-R18, Q21-P18, Q20-N17, Q19-N16, Q18-N18, Q17-M18, Q16-M17, Q15-M16, Q14-L18, Q13-L15, Q12-K16, Q11- L16, Q10-L17, Q9-K18, Q8-K17, Q7-K15, Q6-J15, Q5-J16, Q4-J18, Q3-J17, Q2-H15, Q1-H16, Q0-H18 Power E(8-13), F(6-13), G(6,7,12-14), H6, J6, K6, L(6,7), M(6-8), N(6-11), R(4,5), T(1-5), U(3-5), V(3,4)
D[47:0]
Data Inputs
DQ[63:0] Memory Data Bus
DQS[7:0] Memory Data Strobe Q[47:0] Data Outputs
VCC
Core VCC & Output voltage for DDR SDRAM Output rail voltage for I/Os Ground Pin Do Not Connect
VDDQ GND DNC
Power Ground --
H(13,14), J(13,14), K(13,14), L(13,14), M(12-14), N(12,13) G(8-11), H(7-12), J(7-12), K(7-12), L(8-12), M(9-11), P8 P13, R(13,14), T(13,14,16), U(14-16), V(14-16)
10 JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DETAILED DESCRIPTIONS
SEQUENTIAL FLOW-CONTROL STRUCTURE The IDT sequential flow-control (SFC) device is comprised of three interfaces: input port, output port, and memory interface. The input and output port can operate independently of each other with selectable bus widths of x12, x24, or x48 bits wide. The third interface, or memory interface, is connected directly to an external memory, which can be used to offload data entering the SFC device. WRITING AND READING FROM THE SEQUENTIAL FLOW-CONTROL DEVICE Writing into the SFC device is accomplished by setting the write enable signal (WEN) and write chip select (WCS) low with a free running write clock (WCLK). Data will be written on the rising edge of every WCLK into the Quad-Port (QP) cache of the SFC device. The internal state machine of the device will determine whether to send the data to the DDR SDRAM or send it directly through to the output bus, depending on when the data is to be accessed. This provides "data coherency" and minimizes the path that the data has to travel.
Reading from the SFC device is accomplished by setting the read enable signal (REN) and read chip select (RCS) low with a free running read clock (RCLK). Data will be sent to the output bus on the rising edge of every RCLK. This data will be accessed either from the QP cache or the external DDR SDRAM. EXTERNAL MEMORY SELECTION The DDR SDRAM interface of the SFC device can support DDR SDRAM with standard DDR I specifications. The SFC device can support any external memory within the following characteristics:
* * *
Bus width: 16-bit or 32-bit wide Speed: 133MHz or 166MHz Density: 128Mb or 256Mb
Table 1 lists the DDR SDRAM minimum specifications that are required to meet the sequential flow-control device requirements. Table 2 lists the memory vendors and associated part numbers of DDR SDRAMs that have been validated by IDT to meet the requirements for the DDR SDRAM interface.
TABLE 1 - DDR SDRAM MINIMUM SPECIFICATIONS
DDR SDRAM Minimum Specifications Symbol tCK tRFC tRCD tRP tWR tRCDRD tRCDWR CL = 2.5 CL = 3.0 Parameter Clock cycle time Auto refresh command period Active to read/write delay Precharge comman period Write recovery time Active to read delay Active to write delay 16-bit DDR SDRAM 6 n/a 75 20 20 15 n/a n/a 32-bit DDR SDRAM n/a 6 63 n/a 18 1.5 18 9 Units ns ns ns ns ns ns ns
NOTE: 1. These are the minimum specifications that the DDR SDRAM must meet.
TABLE 2 - SUPPORTED MEMORY VENDORS
Density 128Mb 256Mb 256Mb 256Mb 256Mb Bus Width 32 16 16 16 32 Vendor Samsung Samsung Micron Infineon Samsung Part# K4D263238"X"-GC45 K4H561638"X"-TCLB3 K4H561638"X"-GCLB3 MT46V16M16TG-6T MT46V16M16TG-75 HYB25D256160BTL-6 HYB25D256160BTL-7 K4D553238"X"-JC50
NOTES: 1. The part numbers listed above include packages that are recommended and validated by IDT. Other packages (such as lead free PCB, FBGA, etc.) may also be used but have not been validated by IDT. 2. The letter "X" for Samsung memory part numbers denotes the latest die revision for that particular device. Check with Samsung for the latest updated part number.
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JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
* Two 16-bit devices connecting a x32 interface to the DDR SDRAM * Two 32-bit devices connecting a x36 interface to the DDR SDRAM * Two 32-bit devices connecting a x64 interface to the DDR SDRAM * Three 16-bit devices connecting a x36 interface to the DDR SDRAM * Four 16-bit devices connecting a x64 interface to the DDR SDRAM
EXTERNAL MEMORY CONFIGURATIONS The DDR SDRAM interface of the sequential flow-control (SFC) device has a 64-bit output data bus that provides up to four (16-bit SDRAM) external DDR SDRAM connections. For multiple memory connections, they must be of the same density configuration and speed grade. For example, two device connected cannot consist of one 128Mb and one 256Mb memory nor two 128Mb with one at 100MHz and the other at 133MHz. Below is a summary of the possible configurations:
* One 16-bit device connecting a x16 interface to the DDR SDRAM * One 32-bit device connecting a x32 interface to the DDR SDRAM
These various configurations determine the storage density of the SFC device. The storage density can range from a minimum of 128Mb to a maximum of 1Gb. Table 3 lists the possible ways to connect the DDR SDRAMs and the number of chipset solutions to obtain the various storage densities.
TABLE 3 - TOTAL POSSIBLE EXTERNAL MEMORY CONFIGURATIONS
Two Chip Solution(1) Configuration 1, 2 1 x128Mb [4M x 32] Total memory: 128Mb 1 x 256Mb [8M x 32] Total memory: 256Mb 1 x 128Mb [8M x 16] Total memory: 128Mb 1 x 256Mb [16M x 16] Total memory: 256Mb
(2)
Three Chip Solution(1)
(2)
Four Chip Solution(1)
(2)
Five Chip Solution(1)
(2)
Configurations 3, 4, 5 2 x 128Mb [4M x 32] Total memory: 256Mb 2 x 256Mb [8M x 32] Total memory: 512Mb 2 x 128Mb [8M x 16] Total memory: 256Mb 2 x 256Mb [16M x 16] Total memory: 512Mb
Configuration 6 N/A N/A
Configuration 7 N/A N/A
3 x 128Mb [8M x 16] Total memory: 384Mb 3 x 256Mb [16M x 16] Total memory: 768Mb
4 x 128Mb [8M x 16] Total memory: 512Mb 4 x 256Mb [16M x 16] Total memory: 1Gb
NOTES: 1. The chip solution number includes the sequential flow-control device and external DDR SDRAM 2. See Figure 2a-2g for the 7 different configurations referenced in the table above.
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JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONNECTING THE DDR SDRAM Below are the various chipset solution configurations available to the sequential flow-control device (see Figure 2a-2g). The external memory interface is designed to seamlessly connect one or more DDR SDRAMs. The output signal names should be connected directly to its corresponding input signal on the DDR SDRAM. There are three signals on the DDR SDRAM that must be tied to a static state. CKE, CS, and DM. Table 4 outlines how to connect the many interface pins to the DDR SDRAM(s). Figure 3 and 4 are some examples of the memory interface connections for various density configurations. For information on DDR SDRAM layout recommendations, please see IDT application note AN-423.
DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32] Total Memory Density: 256Mb or 512Mb Useable Memory(2): 108Mb or 252Mb
4 12 Data Bus 36 32 128Mb or 256Mb DDR SDRAM
6358 drw07
IDT SFC
Address Bus 12
Figure 2d. Configuration 4 - Three Chip Solution DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32] Total Memory Density: 128Mb or 256Mb Useable Memory(2): 108Mb or 252Mb
DDR SDRAM: 256Mb [16Mb x 16] Total Memory Density: 512Mb Useable Memory(2): 504Mb
16 13 Data Bus 32 16
IDT SFC
Data Bus 32 Address Bus 12
128Mb or 256Mb DDR SDRAM
6358 drw04
IDT SFC
256Mb DDR SDRAM
Figure 2a. Configuration 1 - Two Chip Solution
Address Bus 13
6358 drw08
Figure 2e(1). Configuration 5 - Three Chip Solution DDR SDRAM: 256Mb [16Mb x 16] Total Memory Density: 256Mb Useable Memory(2): 216Mb
IDT SFC
Data Bus 16 Address Bus 13
DDR SDRAM: 256Mb [16Mb x 16] Total Memory Density: 768Mb Useable Memory(2): 567Mb
256Mb DDR SDRAM
4 13 16 13
6358 drw05
IDT SFC
Data Bus 36 16
Figure 2b(1). Configuration 2 - Two Chip Solution
256Mb DDR SDRAM
Address Bus 13
6358 drw09
DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32] Total Memory Density: 256Mb or 512Mb Useable Memory(2): 216Mb or 504Mb
32 12 Data Bus 64 32 128Mb or 256Mb DDR SDRAM
Figure 2f . Configuration 6 - Four Chip Solution
(1)
DDR SDRAM: 256Mb [16Mb x 16] Total Memory Density: 1Gb Useable Memory(2): 1008Mb
16 13
IDT SFC
Address Bus 12
Data Bus
6358 drw06
IDT SFC
64
16
Figure 2c. Configuration 3 - Three Chip Solution
NOTES: 1. * 12-bit address bus for 8Mb x16 * 13-bit address bus for 16Mb x16 2. Refer to Total Available Memory Usage section for details.
Address Bus 13
256Mb DDR SDRAM
6358 drw10
Figure 2g . Configuration 7 - Five Chip Solution
13 JULY 29, 2004
(1)
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 4 - SFC TO DDR SDRAM INTERFACE CONNECTIONS
32 12
IDT SFC
Data Bus 32 Address Bus 12
128Mb or 256Mb DDR SDRAM
6358 drw04
IDT SFC
Data Bus 64 32
Address Bus 12
128Mb or 256Mb DDR SDRAM
6358 drw06
CONFIGURATION 1 SFC Outputs DDR SDRAM DQ[31:0] DQS[3:0] A[11:0] CK, CK RAS, CAS BA[1:0] WE DQ[31:0] DQS[3:0] A[11:0] CK, CK RAS, CAS BA[1:0] WE CONFIGURATION 3 SFC Outputs DDR SDRAM #1 DQ[31:0] DQ[31:0] DQ[63:32] -DQS[3:0] DQS[3:0] DQS[7:4] -A[11:0] A[11:0] CK, CK CK, CK RAS, CAS RAS, CAS BA[1:0] BA[1:0] WE WE DDR SDRAM Hard wired pins CKE VCC CS GND DM[3:0] GND SFC Hard wired pins A12 VCC
DDR SDRAM Hard wired pins CKE VCC CS GND DM[3:0] GND SFC Hard wired pins DQ[63:32] VCC DQS[7:4] VCC A12 VCC
DDR SDRAM #2 -DQ[31:0] -DQS[3:0] A[11:0] CK, CK RAS, CAS BA[1:0] WE
4 12 Data Bus 36 32 128Mb or 256Mb DDR SDRAM
6358 drw07
IDT SFC
Data Bus 16 Address Bus 13
256Mb DDR SDRAM
IDT SFC
Address Bus 12
CONFIGURATION 4
6358 drw05
CONFIGURATION 2 SFC Outputs DDR SDRAM DQ[15:0] DQ[15:0] DQS0 LDQS DQS1 UDQS A[12:0] A[12:0] CK, CK CK, CK RAS, CAS RAS, CAS BA[1:0] BA[1:0] WE WE DDR SDRAM Hard wired pins CKE VCC CS GND LDM GND UDM GND SFC Hard wired pins DQ[63:16] VCC DQS[7:2] VCC
14
SFC Outputs DQ[31:0] DQ[35:32] DQ[63:36] DQS[3:0] DQS[7:4] A[11:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM #1 DQ[31:0] --DQS[3:0] -A[11:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM #2 -DQ[3:0] --DQS[3:0] A[11:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM Hard wired pins CKE VCC CS GND DM[3:0] GND DQ[31:4] VCC SFC Hard wired pins A12 VCC
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 4 - SFC TO DDR SDRAM INTERFACE CONNECTIONS(Continued)
CONFIGURATION 5
16 13 Data Bus 32 16
IDT SFC
256Mb DDR SDRAM
Address Bus 13
6358 drw08
SFC Outputs DQ[15:0] DQ[31:16] DQS0 DQS1 A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM #1 DQ[15:0] -LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM #2 -DQ[15:0] LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM Hard wired pins CKE VCC CS GND LDM GND UDM GND SFC Hard wired pins DQ[63:32] VCC DQS[7:2] VCC
CONFIGURATION 6
4 13 16 13
IDT SFC
Data Bus 36 16
256Mb DDR SDRAM
Address Bus 13
6358 drw09
SFC Outputs DQ[15:0] DQ[31:16] DQ[35:32] DQS0 DQS1 A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM #1 DQ[15:0] --LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM #2 -DQ[15:0] -LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM #3 --DQ[3:0] LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM Hard wired pins CKE VCC CS GND LDM GND UDM GND DQ[15:4] VCC SFC Hard wired pins DQ[63:36] VCC DQS[7:2] VCC
15
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 4 - SFC TO DDR SDRAM INTERFACE CONNECTIONS(Continued)
16
13
Data Bus
IDT SFC
64
16
Address Bus 13
256Mb DDR SDRAM
6358 drw10
CONFIGURATION 7 SFC Outputs DQ[15:0] DQ[31:16] DQ[51:32] DQ[63:52] DQS0 DQS1 A[12:0] CK, CK RAS, CAS BA[1:0] WE DDR SDRAM #1 DQ[15:0] ---LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE DDR SDRAM #2 -DQ[15:0] --LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE DDR SDRAM #3 --DQ[15:0] -LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE DDR SDRAM #4 ---DQ[15:0] LDQS UDQS A[12:0] CK, CK RAS, CAS BA[1:0] WE
DDR SDRAM Hard wired pins CKE VCC CS GND LDM GND UDM GND SFC Hard wired pins DQS[7:2] VCC
16
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Sequential Flow-Control Device
CK CK DQS[3:0] WE CAS RAS DQ[31:0] A[11:0] 4 CK CK
DDR SDRAM 2M x 16 x 4 128M
DQS[3:0] WE CAS RAS DQ[31:0] A[11:0] CKE DM[3:0] CS
6358 drw11
VCC
32 12
Figure 3. Memory Interface Connection (Single Chip)
Sequential Flow-Control Device
CK CK DQS[7:0] WE CAS RAS DQ[31:0] A[11:0] 8 4 CK CK
DDR SDRAM 8M x 32 256M
DQS[3:0] WE CAS RAS DQ[31:0] A[11:0] CKE DM[3:0] CS
VCC
64 12
32 12
CK CK 4 DQS[3:0] WE CAS RAS 32 12 DQ[31:0] A[11:0] DM[3:0] CS
6358 drw12
VCC CKE
Figure 4. Memory Interface Connection (Two Chip)
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JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TOTAL AVAILABLE MEMORY USAGE The sequential flow-control (SFC) is designed to efficiently use as much of the DDR SDRAM memory as possible, but due to the discontinuity between the SFC bus width (x48) and the DDR SDRAM interface (x16 or x32), some columns in a row of the SDRAM will not be used. As a result, the total usable memory will be slightly less than the total available memory in the SDRAM. Table 5 outlines the total usable memory for the various configurations depending on
whether or not the Error Detection and Correction (EDC) feature is selected. If the EDC feature is selected, 8 syndrome bits will be generated per every 64 bits of data. Therefore every third write burst to the SDRAM will send out the 8 syndrome bits, resulting in 24 unused bits in the column. Therefore, using the EDC feature, there will be significantly less usable memory of data storage. The EDC function is described in the Error Detection and Correction section of this datasheet.
TABLE 5 - TOTAL USEABLE MEMORY BASED ON VARIOUS CONFIGURATIONS
Total DDR SDRAM Density Configuration 1 1 x [4Mb x 32] 1 x [8Mb x 32] Configuration 2 1 x [16Mb x 16] Configuration 3 2 x [4Mb x 32] 2 x [8Mb x 32] Configuration 4 2 x [4Mb x 32] 2 x [8Mb x 32] Configuration 5 2 x [8Mb x 16] Configuration 6 3 x [8Mb x 16] 3 x [16Mb x 16] Configuration 7 4 x [16Mb x 16] 128Mb 256Mb 256Mb 256Mb 512Mb 256Mb 512Mb 256Mb 384Mb 768Mb 1Gb Total Usable Memory (EDC off) 108Mb 252Mb 216Mb 216Mb 504Mb 122Mb 284Mb 252Mb 284Mb 567Mb 1008Mb Total Usable Memory (EDC on) 72Mb 144Mb 144Mb 144Mb 288Mb 108Mb 252Mb 144Mb 252Mb 504Mb 576Mb
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JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAXIMUM I/O OPERATING FREQUENCY The sequential flow-control (SFC) device is designed to operate at the maximum frequency of 133MHz. There are certain configurations however, that can increase or decrease the maximum frequency of the input and output ports. In some configurations (e.g. x24 I/O width), the I/O speeds can run up to
166MHz. The main factors that determine the usable memory are the I/O buswidth of the SFC, the density and number of DDR SDRAMs connected, and whether or not EDC is used. Tables 6 and 7 lists the maximum frequency for the input and output ports of the SFC based on the various configurations.
TABLE 6 - IDT72T6480 MAXIMUM FREQUENCY BASED ON 166MHz DDR SDRAM
Configuration Configuration Configuration Configuration Configuration Configuration Configuration 1 2 3 4 5 6 7 Bus-Width x48 EDC On EDC Off 50MHz 66MHz 33MHz 33MHz 100MHz 133MHz 66MHz 66MHz 50MHz 66MHz 66MHz 66MHz 100MHz 133MHz Bus-Width x24 EDC On EDC Off 100MHz 133MHz 66MHz 66MHz 166MHz 166MHz 133MHz 133MHz 100MHz 133MHz 133MHz 133MHz 166MHz 166MHz Bus-Width x12 EDC On EDC Off 166MHz 166MHz 133MHz 133MHz 166MHz 166MHz 166MHz 166MHz 166MHz 166MHz 166MHz 166MHz 166MHz 166MHz
TABLE 7 - IDT72T6480 MAXIMUM FREQUENCY BASED ON 133MHz DDR SDRAM
Configuration Configuration Configuration Configuration Configuration Configuration Configuration 1 2 3 4 5 6 7 Bus-Width x48 EDC On EDC Off 33MHz 50MHz 25MHz 25MHz 66MHz 100MHz 50MHz 50MHz 33MHz 50MHz 50MHz 50MHz 66MHz 100MHz Bus-Width x24 EDC On EDC Off 66MHz 100MHz 50MHz 66MHz 133MHz 166MHz 100MHz 100MHz 66MHz 100MHz 100MHz 100MHz 133MHz 166MHz Bus-Width x12 EDC On EDC Off 133MHz 166MHz 100MHz 133MHz 166MHz 166MHz 166MHz 166MHz 133MHz 166MHz 166MHz 166MHz 166MHz 166MHz
19
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ERROR DETECTION AND CORRECTION The Error Detection and Correction (EDC) feature is available to ensure data integrity between the DDR SDRAM interface and the SFC. The EDC corrects all single bit hard and soft errors that are accessed from the DDR SDRAM. Multiple bit errors are not detected nor corrected. The EDC logic blocks consist of a check bit generator and error detection correction logic. When the EDC is enabled, the check bit generator will generate 8 syndrome bits on the 8-byte boundary. The 8 syndrome bits are written into the DDR SDRAM along with the data. The SFC will burst write two cycles for data, and one cycle for syndrome bits. In order to minimize overhead and
increase throughput, not all memory in the DDR SDRAM is utilized. Table 5 lists the total usable memory for all 7 configurations when the EDC is enabled. When a read operation is performed, the syndrome bits will be transferred to the error detection correction logic block and decoded to determine whether there are any single bit errors on the data. Single bit errors will be corrected and data is passed through to the QP cache. The EDC is enabled using the MIC[2:0] pins. When the EDC is enabled, the dynamics of the total usable memory in the DDR SDRAM and the SFC operating speed will vary, listed in Tables 6 and 7. Table 8 shows how to enable the EDC feature for the 7 configurations
TABLE 8 - MIC[2:0] CONFIGURATIONS
Configuration Configuration Configuration Configuration Configuration Configuration Configuration 1 2 3 4 5 6 7 EDC Off MIC [2:0] = 000 MIC [2:0] = 001 MIC [2:0] = 111 MIC [2:0] = 100 MIC [2:0] = 000 MIC [2:0] = 100 MIC [2:0] = 111 EDC On MIC [2:0] = 010 MIC [2:0] = 011 MIC [2:0] = 101 MIC [2:0] = 110 MIC [2:0] = 010 MIC [2:0] = 110 MIC [2:0] = 101
20
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SETTING THE MEMORY INTERFACE SIGNALS The configurations listed in Figure 2a-2g can be programmed into the sequential flow-control device by using the MIC[2:0], MTYPE[1:0], and
MSPEED. For information about these signals, please refer to the Signal Description section. Table 9 is a list that shows the settings for the different configurations.
TABLE 9 - MEMORY CONFIGURATIONS SETTINGS
MIC[2:0] Configuration 1 Configuration 2 Configuration 3 Configuration 4 Configuration 5 Configuration 6 Configuration 7 000 - EDC Off 010 - EDC On 001 - EDC Off 011 - EDC On 111 - EDC Off 101 - EDC On 110 - EDC Off 100 - EDC On 000 - EDC Off 010 - EDC On 110 - EDC Off 100 - EDC On 111 - EDC Off 101 - EDC On MTYPE[1:0] 00 - (4Mb x 32) 10 - (8Mb x 32) -- 11 - (16Mb x 16) 00 - (4Mb x 32) 10 - (8Mb x 32) 00 - (4Mb x 32) 10 - (8Mb x 32) -- 11 - (16Mb x 16) -- 11 - (16Mb x 16) -- 11 - (16Mb x 16) MSPEED 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 - 166MHz 0 - 133MHz 1 -166MHz 0 - 133MHz 1 - 166MHz
21
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 10 - DEVICE CONFIGURATION
Signal Pins Static State ASYR ASYW BM[3:0] FSEL[1:0] 0 1 0 1 -- 00 01 10 11 0 1 0 1 0 1 0 1 -- 0 1 00 01 10 11 Configuration Read port configured in asynchronous mode Read port configured in synchronous mode Write port configured in asynchronous mode Write port configured in synchronous mode See Table 13 - Bus-Matching Configurations Programmable flag register offset value = 127 Programmable flag register offset value = 1,023 Programmable flag register offset value = 4,095 Programmable flag register offset value = 16,383 IDT Standard mode FWFT mode Depth expansion in FWFT mode Depth expansion in IDT Standard mode I/O voltage set to 3.3V levels I/O voltage set to 2.5V levels JTAG function is disabled JTAG function is enabled See Table 8 - MIC[2:0] Configurations for description External memory interface clocks set to 133MHz External memory interface clocks set to 166MHz External memory configuration is: 4M x 32 Not used External memory configuration is: 8M x 32 External memory configuration is: 16M x 16
FUNCTIONAL DESCRIPTIONS
MASTER RESET AND DEVICE CONFIGURATION During master reset the sequential flow-control configuration and settings are determined, this includes the following: 1. Synchronous or Asynchronous read and write port operation 2. Bus-width configuration 3. Default offset register values 4. IDT standard or first word fall through (FWFT) timing mode 5. Depth expansion in IDT standard or FWFT mode 6. I/O voltage set to 2.5V or 3.3V levels 7. JTAG function enabled or disabled 8. Configuration of the external memory interface The state of the configuration inputs during master reset will determine which of the above modes are selected. A master reset comprises of pulsing the MRS input pin from high to low for a period of time (tRS) with the configuration inputs held in their respective states. Table 10, Device Configuration summarizes the configuration modes available during master reset. These signals are described in detail in the signal description section. PROGRAMMABLE ALMOST EMPTY/ALMOST FULL FLAGS The SFC has a set of programmable flags (PAE/PAF) that can be used as an early indicator for the empty and full boundary conditions. These flags have an offset value (n, m) that will determine the almost empty and almost full boundary conditions. There are four default offset values selectable during master reset, these values are shown in Table 11, Default Programmable Flag Offsets. Offset values can also be programmed using the serial programming pins (SCLK, SI, and SWEN). The SFC has two internal offset registers that are used to store the specific offset value, one for the PAE and one for the PAF. The total number of bits (shown in Table 12, Number of Bits Required for Offset Registers) must be completely programmed to the offset registers. The serial programming sequence begins by writing data into the PAE register followed by the PAF register. See Figure 29, Serial Loading of Programmable Flag Registers for the associated timing diagram. The total number of bits required to program the offset registers will vary depending on the type of configuration that is shown in Figure 2a-2g, the bus-width selected, and whether EDC is used. The values of n, m are used such that the PAE will become active (LOW) when there are at least one to n words written in the device. Similarly PAF will become active (LOW) when there are at least D - M words or more in the device, where D is the density of the SFC.
FWFT IDEM IOSEL JSEL MIC[2:0] MSPEED MTYPE[1:0]
TABLE 11- DEFAULT PROGRAMMABLE FLAG OFFSETS
FSEL1 0 0 1 1 FSEL0 0 1 0 1 Offset n,m 127 1,023 4,095 16,383
TABLE 12- NUMBER OF BITS REQUIRED FOR OFFSET REGISTERS
Write Port Bus-Width Configuration 1 (128Mb) Configuration 1 (256Mb) Configuration 2 (256Mb) Configuration 3 (256Mb) Configuration 3 (512Mb) Configuration 4 (256Mb) Configuration 4 (512Mb) Configuration 5 (512Mb) Configuration 6 (768Mb) Configuration 7 (1Gb) EDC On 21 22 22 22 23 22 23 23 24 24 x48 EDC Off 22 23 23 23 24 22 23 24 24 25 EDC On 22 23 23 23 24 23 24 24 25 25 22 x24 EDC Off 23 24 24 24 25 23 24 25 25 26 EDC On 23 24 24 24 25 24 25 25 26 26 x12 EDC Off 24 25 25 25 26 24 25 26 26 27 JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS INPUTS
DATA INPUTS (D0 - D47) Data inputs for 48-bit wide data (D0 - D47), data inputs for 24-bit wide data (D0 - D23) or data inputs for 12-bit wide data (D0 - D11).
CONTROLS
MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is toggled LOW then HIGH. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW, PAF will go HIGH. If FWFT is LOW during Master Reset then the IDT Standard mode, along with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with IR and OR, are selected. OR will go HIGH and IR will go LOW. All configuration control signals must be set prior to the LOW to HIGH transition of MRS. During a Master Reset, the output register is initialized to all zeroes. A Master Reset is required after power up, before a write operation can take place. MRS is an asynchronous function. See Figure 6, Master Reset and Initialization, for the relevant timing diagram. PARTIAL RESET (PRS) A Partial Reset is accomplished whenever the PRS input is toggled LOW then HIGH. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes LOW, and PAF goes HIGH. Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH, and IR will go LOW. Following Partial Reset, all values held in the offset registers remain unchanged. The output register is initialized to all zeroes. PRS is asynchronous. A Partial Reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient. See Figure 7, Partial Reset, for the relevant timing diagram. ASYNCHRONOUS WRITE (ASYW) The write port can be configured for either synchronous or asynchronous mode of operation. If during Master Reset the ASYW input is LOW, then asynchronous operation of the write port will be selected. During asynchronous operation of the write port the WCLK input becomes WR input, this is the asynchronous write strobe input. A rising edge on WR will write data present on the data inputs into the sequential flow-control device (SFC). (WEN must be LOW when using the write port in asynchronous mode). When the write port is configured for asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissable. The full flag (FF) and programmable almost full flag (PAF) operates in an asynchronous manner, that is, the full flag and PAF flag will be updated based in both a write operation and read operation. Note, if asynchronous mode is selected, FWFT is not permissible. Refer to Figure 24, Asynchronous Write and PAE flag - IDT Standard mode and Figure 25, Asynchronous Write and PAF flag - IDT Standard mode for relevant timing and operational waveforms. ASYNCHRONOUS READ (ASYR) The read port can be configured for either synchronous or asynchronous mode of operation. If during a Master Reset the ASYR input is LOW, then
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asynchronous operation of the read port will be selected. During asynchronous operation of the read port the RCLK input becomes RD input, this is the asynchronous read strobe input. A rising edge on RD will read data from the SFC via the output register and data output port. (REN must be tied LOW during asynchronous operation of the read port). The OE input provides three-state control of the Qn output bus, in an asynchronous manner. When the read port is configured for asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissible if the read port is asynchronous. The Empty Flag (EF) and programmable almost empty flag (PAF) operates in an asynchronous manner, that is, the empty flag and PAE will be updated based on both a read operation and a write operation. Refer to Figure 23, Asynchronous Read and PAF flag - IDT Standard mode, Figure 26, Asynchronous Empty Boundary - IDT Standard mode, Figure 27, Asynchronous Full Boundary - IDT Standard mode,, and Figure 28, Asynchronous Read and PAE flag - IDT Standard mode, for relevant timing and operational waveforms. FIRST WORD FALL THROUGH (FWFT) During Master Reset, the state of the FWFT input determines whether the device will operate in IDT standard mode or First Word Fall Through (FWFT) mode. If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the SFC. It also uses the Full Flag function (FF) to indicate whether or not the SFC has any free space for writing. In IDT Standard mode, every word read from the SFC, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the SFC has any free space for writing. In the FWFT mode, the first word written to an empty SFC goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. WRITE STROBE AND WRITE CLOCK (WR/WCLK) If synchronous operation of the write port has been selected via ASYW, this input behaves as WCLK. A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met with respect to the LOW-to-HIGH transition of the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/IR, and PAF flags will not be updated. The Write and Read Clocks can either be independent or coincident. If asynchronous operation has been selected this input is WR (write strobe). Data is asynchronously written into the SFC via the Dn inputs whenever there is a rising edge on WR. In this mode the WEN input must be LOW. WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the SFC on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is HIGH, no new data is written in the SFC. To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to occur. The FF is updated by two WCLK cycles + tSKEW after the RCLK cycle.
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To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + tSKEW after the valid RCLK cycle. WEN is ignored when the SFC is full in either FWFT or IDT Standard mode. If asynchronous operation of the write port has been selected, then WEN must be held active. READ STROBE AND READ CLOCK (RD/RCLK) If synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge of the RCLK input. It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR and PAE flags will not be updated. The Write and Read Clocks can be independent or coincident. If asynchronous operation has been selected this input is RD (Read Strobe). Data is asynchronously read from the SFC whenever there is a rising edge on RD. In this mode the REN and RCS inputs must be tied LOW. The OE input is used to provide asynchronous control of the three-state Qn outputs. WRITE CHIP SELECT (WCS) The WCS disables all Write data operations (data only) if it is held HIGH. To perform normal operations on the write port, the WCS must be enabled, held LOW. READ ENABLE (REN) When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and then no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. In the IDT Standard mode, every word accessed at Qn, including the first word written to an empty cache, must be requested using REN provided that RCS is LOW. When the last word has been read from the SFC, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the SFC is empty. Once a write is performed, EF will go HIGH allowing a read to occur. The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle. Both RCS and REN must be active, LOW for data to be read out on the rising edge of RCLK. In the FWFT mode, the first word written to an empty SFC automatically goes to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW after the first write. REN and RCS do not need to be asserted LOW for the First Word to fall through to the output register. In order to access all other words, a read must be executed using REN and RCS. The RCLK LOW-to-HIGH transition after the last word has been read from the SFC, Output Ready (OR) will go HIGH with a true read (RCLK with REN = LOW;RCS = LOW), inhibiting further read operations. REN is ignored when the SFC is empty. If asynchronous operation of the Read port has been selected, then REN must be held active, (LOW). OUTPUT ENABLE (OE) When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes into a high impedance state. During Master or a Partial Reset the OE is the only input that can place the output bus Qn, into High-Impedance. During Reset the RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT (RCS) The Read Chip Select input provides synchronous control of the Read output port. When RCS goes LOW, the next rising edge of RCLK causes the Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only input that provides High-Impedance control of the Qn outputs. If OE is LOW the Qn data outputs will be Low-Impedance regardless of RCS until the first rising edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs will go to HighImpedance. The RCS input does not effect the operation of the flags. For example, when the first word is written to an empty SFC, the EF will still go from LOW to HIGH based on a rising edge of RCLK, regardless of the state of the RCS input. Also, when operating the SFC in FWFT mode the first word written to an empty SFC will still be clocked through to the output register based on RCLK, regardless of the state of RCS. For this reason the user must take care when a data word is written to an empty SFC in FWFT mode. If RCS is disabled when an empty SFC is written into, the first word will fall through to the output register, but will not be available on the Qn outputs which are in HIGH-Z. The user must take RCS active LOW to access this first word, place the output bus in LOW-Z. REN must remain disabled HIGH for at least one cycle after RCS has gone LOW. A rising edge of RCLK with RCS and REN active LOW, will read out the next word. Care must be taken so as not to lose the first word written to an empty SFC when RCS is HIGH. See Figure 15 for Read Chip Select. If asynchronous operation of the Read port has been selected, then RCS must be held active, (tied LOW). OE provides three-state control of Qn. BUS-MATCHING (BM[3:0]) These pins are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. All flags will operate on the word/byte size boundary as defined by the selection of bus width. See Figures 17-20 for Bus-Matching Configurations. See Table 13, BusMatching Configurations for the available configurations.
TABLE 13 - BUS-MATCHINGS
BM3 1 1 1 1 1 0 0 0 0 BM2 0 0 1 0 1 0 1 0 1 BM1 0 0 0 1 1 0 0 0 1 BM0 0 1 1 1 1 1 1 1 1 Read Bus Width x48 x24 x12 x48 x48 x24 x12 x24 x12 Write Bus Width x48 x48 x48 x24 x12 x24 x24 x12 x12
FLAG SELECT (FSEL[1:0]) During master reset, these inputs will select one of four default values for the programmable flags PAE and PAF. The selected value (listed in Table 14 MTYPE[1:0] Configurations) will apply to both PAE and PAF offset.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MEMORY CONFIGURATION (MIC[2:0]) These signals enable the EDC feature of the device. See Table 8, MIC[2:0] Configurations for more information. MEMORY SPEED (MSPEED) This pin is used to determine the memory interface clock speed (CK and CK) for the external memory used. If MSPEED is HIGH, external memory CK and CK will be operating at 166MHz. If MSPEED is LOW, then the external memory CK and CK will be operating at 133MHz. MASTER CLOCK (MCLK) 33MHz reference clock used to generate CK and CK for external memory interface. MEMORY TYPE (MTYPE[1:0]) These signals select the density configuration of the external DDR SDRAM used. See Table 14, MTYPE[1:0] Configurations for selection of the memory density configuration.
modes. See Figure 29, Serial Loading of Programmable Flag Registers, for the timing diagram. I/O VDDQ SELECT (IOSEL) This input determines whether the inputs and outputs will tolerate a 2.5V or 3.3V voltage signals. If IOSEL is HIGH, then all I/Os will be 2.5V levels. If IOSEL is LOW, then all I/Os will be 3.3V levels. See Table 15, Parameters affected by I/O selection for a list of affected I/O signals.
TABLE 15 - PARAMETERS AFFECTED BY I/O SELECTION
SFC I/O affected by I/O selection ASYR ASYW BM[3:0] D[47:0] EF/OR FF/IR FSEL[1:0] FWFT IDEM IOSEL JSEL MIC[2:0] MCLK MRS MSPEED MTYPE[1:0] OE PAE PAF PRS Q[47:0] RCLK/RD RCS REN SREN SWEN TCK/SCLK TDI/SI TDO/SO TMS WCLK/WR WCS WEN DDR SDRAM I/O NOT affected(1) A[12:0] DQ[63:0] BA[1:0] DQS[7:0] CK RAS CK WE CAS
TABLE 14 - MTYPE[1:0] CONFIGURATIONS
Density Configurations 4M x 32 MTYPE0 MTYPE1 0 0 8M x 32 0 1 Reserved 1 0 16M x 16 1 1
NOTE: 1. I/O to DDR SDRAM is not affected by I/O voltage selection
DEPTH EXPANSION MODE SELECT (IDEM) This select pin is used for depth expansion configuration in IDT Standard mode. If this pin is tied HIGH, then the FF/IR signal will be inverted to provide a seamless depth expansion interface. If this pin is tied LOW, the depth expansion in IDT Standard mode will be deactivated. For details on depth expansion configuration, see Figure 34, Depth Expansion Configuration in IDT Standard Mode and Figure 35, Depth Expansion Configuration in FWFT Mode. SERIAL READ ENABLE (SREN) The serial read enable input is an enable used for reading the value of the programmable offset registers. By setting the JSEL pin to LOW, the serial data output (SO) and serial clock (SCLK) signals can be used with SREN to program the offset registers. When SREN is LOW, data at the SO can be read from the offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial read enable is HIGH, the reading of the offset registers will stop. SREN must be kept LOW in order to read the entire contents of the scan out register. If at any point SREN is toggled HIGH, the read pointer of the offset registers will reset to the first location. The next time SREN is enabled the first contents in the offset register will be read back. Serial read enable functions the same way in both IDT Standard and FWFT modes. See Figure 30, Reading of Programmable Flag Registers, for the timing diagram. SERIAL WRITE ENABLE (SWEN) The serial write enable input is an enable used for serial programming of the programmable offset registers. By setting the JSEL pin to LOW, the serial input (SI) and serial clock (SCLK) signals can be used with SWEN to program the offset registers. When SWEN is LOW, data at the SI input are loaded into the offset register, one bit for each LOW-to-HIGH transition of SCLK. When SWEN is HIGH, the offset registers retain the previous settings and no offsets are loaded. Serial write enable functions the same way in both Standard IDT and FWFT
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JTAG SELECT (JSEL) This input determines whether the JTAG port will be activated or deactivated. If JSEL is HIGH, then the JTAG port is activated and the associated JTAG pins (TCK, TDI, TDO, TMS) are used for the boundary-scan function. If JSEL is LOW, the JTAG port is disabled and the serial programming pins (SCLK, SI, SO) will be used to program and read the offset register values for PAE and PAF. See Figure 29 and 30, Serial Loading and Reading of Programmable Registers for information on how to program the registers.
OUTPUTS
FULL FLAG/INPUT READY (FF/IR) This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function is selected. When the SFC is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the SFC is not full. If no reads are performed after a reset (either MRS or PRS), FF will go LOW See Figure 12, Full Boundary - IDT Standard Mode, for the relevant timing information. In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR will go HIGH see Figure 9 Write First Word Cycles - FWFT Mode, for the relevant timing information. The IR status not only measures the contents of the SFC memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to de-assert IR is one greater than needed to assert FF in IDT Standard mode. FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs.
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EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the SFC is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the SFC is not empty. Figure 10, Empty Boundary - IDT Standard Mode for the relevant timing information. In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty SFC appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the SFC to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes LOW again. See Figure 11, Empty Boundary (FWFT Mode), for the relevant timing information. EF/OR is synchronous and updated on the rising edge of RCLK. In IDT Standard mode, EF is a double register-buffered output. In FWFT mode, OR is a triple register-buffered output. PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full flag (PAF) will go LOW when the SFC reaches the almost-full condition. In IDT Standard mode, if no reads are performed after reset (MRS), PAF will go LOW after (D - m) words are written to the SFC. See Figure 22, Synchronous PAF Flag - IDT Standard Mode and FWFT Mode, for the relevant timing information. If asynchronous PAF configuration is selected, the PAF is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF configuration is selected, the PAF is updated on the rising edge of WCLK. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The Programmable Almost-Empty flag (PAE) will go LOW when the SFC reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words or less in the SFC. The offset "n" is the empty offset value. The default setting for this value is in Table 10, Device Configuration. In FWFT mode, the PAE will go LOW when there are n+1 words or less in the SFC. See Figure 21, Synchronous PAE Flag - IDT Standard Mode and FWFT Mode, for the relevant timing information. If asynchronous PAE configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE configuration is selected, the PAE is updated on the rising edge of RCLK.
DATA OUTPUTS (Q0-Q47) (Q0-Q47) are data outputs for 48-bit wide data, (Q0 - Q23) are data outputs for 24-bit wide data or (Q0-Q11) are data outputs for 12-bit wide data. MEMORY CLOCK OUTPUT (CK) These signals are to be connected to the external DDR SDRAM's clock input. MEMORY CLOCK OUTPUT INVERTED (CK) These signals are to be connected to the external DDR SDRAM's differential clock input. MEMORY BANK ADDRESS INPUT BIT (BA[1:0]) These signals are to be connected to the external DDR SDRAM's bank address input bits. MEMORY COLUMN ADDRESS STROBE (CAS) These signals are to be connected to the external DDR SDRAM's column address strobe input. MEMORY ADDRESS BUS (A[12:0]) These signals are to be connected to the external DDR SDRAM's address bus. MEMORY WRITE ENABLE (WE) These signals are to be connected to the external DDR SDRAM's write enable. MEMORY ROW ADDRESS STROBE (RAS) These signals are to be connected to the external DDR SDRAM's row address strobe input.
BI-DIRECTIONAL I/O
MEMORY DATA INPUTS/OUTPUTS DQ[63:0] These signals are to be connected to the external DDR SDRAM's data input bus. MEMORY DATA STROBE OUTPUT DQS[7:0] These signals are to be connected to the external DDR SDRAM's data strobe inputs.
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DEVICE CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol VTERM TSTG TJMAX IOUT Rating Terminal Voltage with respect to GND Storage Temperature Maximum Junction Temp. DC Output Current Com'l & Ind'l -0.5 to +3.6(2) -55 to +125 150 -50 to +50 Unit V Symbol CIN
(2,3)
Parameter(1) Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10
(3)
Unit pF pF
C C
mA
COUT(1,2)
10
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Compliant with JEDEC JESD8-5. VCC terminal only.
NOTES: 1. With output deselected, (OE VIH). 2. Characterized values, not currently tested. 3. CIN for Vref is 20pF.
PACKAGE THERMAL DATA
Symbol Parameter Junction to case thermal resistance Junction to air thermal resistance airflow @ 0m/s @ 1m/s @ 2m/s @ 3m/s @ 4m/s @ 5m/s MSL Moisture sensitivity level 27.4 22.8 20.3 19.5 18.2 17.8 3 Industrial/ Commercial 3.8 Unit C/W C/W
JC JA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC AVCC VDDQ GND VREF(1) TA TA Parameter Supply Voltage Analog Supply Voltage Output Rail Voltage for I/Os Supply Ground SSTL_2 Voltage Reference Input Operating Temperature (Commercial) Operating Temperature (Industrial) Min. 2.375 2.375 2.375 0 1.13 0 -40 Typ. 2.5 2.5 -- 0 1.25 -- -- Max. 2.625 2.625 3.45 0 1.38 70 85 Unit V V V V V
C C
NOTE: 1. Typically the value of VREF is expected to be (0.49-0.51) x VCC.
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DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V 0.125V, TA = 0C to +70C;Industrial: VCC = 2.5V 0.125V, TA = -40C to +85C)
I/O Type SFC Input (LVTTL) Symbol ILI VIH VIL SFC Output (LVTTL) ILO VOH VOL IOH IOL DDR SDRAM I/O (SSTL_2)
(1)
Parameter Input leakage current Input High Voltage Input Low Voltage Output leakage current Read/Write interface output logic "1" voltage with IOH1 Read/Write interface output logic "0" voltage with IOL1 Read/Write interface output high current (source current) Read/Write interface output low current (sink current) Memory interface output high current (source current) Memory interface output low current (sink current) Memory Interface Input High Voltage Memory Interface Input Low Voltage Memory Interface Output High Voltage Memory Interface Output Low Voltage VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V
Min. -10 2.0 1.7 -- -0.3 -10 VDDQ - 0.4 VDDQ - 0.4 -- -- -2 -8 8 8 -7.6 7.6 1.7 -0.3 1.5 --
Max. 10 5.5 3.45 0.8 0.7 10 -- -- 0.4 0.4 -- -- -- -- -- -- 3.0 0.7 -- 1.00
Unit A V V V V A V V V V mA mA mA mA mA mA V V V V
IOH IOL VIH VIL VOH VOL
POWER CONSUMPTION
Symbol ICC1(2) ICC2(2) ICC3(2) ISB1
(3)
Parameter Active VCC current Active AVCC current Active VDDQ current Standby VCC current Standby VDDQ current
Min. -- -- -- -- --
Max. 650 18 1 600 1
Unit mA mA mA mA mA
ISB2(3)
General DC Test Conditions * Measurements taken with VCC = 2.625V, OE = HIGH, WCLK = RCLK = 16.7MHz, MCLK = 33.3MHz * Data toggles alternately at 1/2 WCLK and RCLK frequency * 0.4 < VIN < VCC, 0.4 < VOUT < VCC
*
Outputs are unloaded (IOUT = 0)
NOTES: 1. These parameters are compliant under JEDEC standard for SSTL_2 (JESD8-9A). These parameters are classified as SSTL_2 Class I output buffers under section 3.2.1 of JESD8-9A. 2. ICC (active current) is measured with MCLK = 33.3MHz, RCLK = WCLK = 16.7MHz, and alternate 101010 data pattern toggling on the outputs. 3. ISB (standby current) is measured with MCLK = RCLK = WCLK = 0MHz with no output data toggling. 4. VSDREF is the VREF of the DDR SDRAM. It is not to be confused with the VREF of the SFC. 5. The maximum value may not represent the maximum current dissipated from the SFC. ICC values are dependent upon various factors that include: VCC, temperature, capacitive load, frequency, bus-width, and output switching characteristics. For calculating ICC with specific parameters, please contact IDT technical support for assistance.
28
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST CONDITIONS 2.5V LVTTL AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels GND to 2.5V 1ns 1.25V 1.25V
AC TEST LOADS
VDDQ/2 50
I/O
Z0 = 50
10pF
2.5V SSTL AC TEST CONDITIONS
Figure 5a. AC Test Load
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels GND to 2.5V 1ns 1.25V 1.25V
6358 drw13
6
tCD (Typical, ns)
5 4 3 2 1 20 30 50 80 100 Capacitance (pF) 200
6358 drw13a
3.3V LVTTL AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels GND to 3.0V 3ns 1.5V 1.5V
Figure 5b. Lumped Capacitive Load, Typical Derating
29
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) SYNCHRONOUS TIMING
(Commercial: VCC = 2.5V 5%, TA = 0C to +70C;Industrial: VCC = 2.5V 5%, TA = -40C to +85C)
Commercial IDT72T6480L7-5
(x24 or x12 I/O width only)(3) (x48 I/O width only)
Com'l & Ind'l(2) IDT72T6480L10 Max. 133 5 -- -- -- -- -- -- -- -- -- -- -- 15 5 5 34 31.3 0.55 0.55 10 -- -- -- -- -- -- -- 20 5 5 5 5 -- -- -- -- 170 136 -- 7.3 -- 0.55 -- 0.55 Min. -- 1 10 4.5 4.5 3.5 0.5 3.5 0.5 10 15 10 20 -- 1 1 32 29.4 0.45 0.45 -- 100 45 45 15 5 5 5 -- -- -- -- -- 7 10 3.5 0.5 -- 128 -- 7.8 -- 0.45 -- 0.45 Max. 100 6.5 -- -- -- -- -- -- -- -- -- -- -- 15 6.5 6.5 34 31.3 0.55 0.55 10 -- -- -- -- -- -- -- 20 6.5 6.5 6.5 6.5 -- -- -- -- -- 136 -- 7.3 -- 0.55 -- 0.55 Unit MHz ns ns ns ns ns ns ns ns ns ns ns s ns ns ns MHz ns tMCYC tMCYC MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns tCK1 tCK2 tCK1 tCK2
Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSU tRSH tPL tRSF tOHZ tOE fMC tMCYC tMCKH tMCKL fSC tSCLK tSCLKH tSCLKL tSDS tSDH tSENS tSENH tASO tWFFs tREFs tPAFs tPAEs tSKEW1 tSKEW2 tWCSS tWCSH fC1 fC2 tCK1 tCK2 tCKH1 tCKH2 tCKL1 tCKL2
Parameter Synchronous Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width Reset Setup Time Reset Hold Time Reset to PLL Lock Reset to Flag and Output Output enable to High-Z Output Enable Valid Master Clock Cycle Frequency Master Clock Cycle Time Master Clock Cycle HIGH Master Clock Cycle LOW Serial Clock Cycle Frequency Serial Clock Cycle Serial Clock High Serial Clock Low Serial Data Setup Serial Data Hold Serial Enable Setup Serial Enable Hold Serial Output Data Access Time Write Clock to Synchronous FF/IR Read Clock to Synchronous EF/OR WCLK to Synchronous PAF RCLK to Synchronous PAE Skew time between RCLK & WCLK for EF/OR and FF/IR in SDR Skew time between RCLK and WCLK for PAE/PAF WCS Setup Time WCS Hold Time Memory Clock Cycle Frequency at 166MHz Memory Clock Cycle Frequency at 133MHz Memory Clock Cycle Time at 166MHz Memory Clock Cycle Time at 133MHz Memory Clock Cycle HIGH at 166MHz Memory Clock Cycle HIGH at 133MHz Memory Clock Cycle LOW at 166MHz Memory Clock Cycle LOW at 133MHz
Min. -- 1 6 2.7 2.7 2 0.5 2 0.5 10 15 10 20 -- 1 1 32 29.4 0.45 0.45 -- 100 45 45 15 5 5 5 -- -- -- -- -- 4 5 2 0.5 160 128 6.2 7.8 0.45 0.45 0.45 0.45
Max. 166 4 -- -- -- -- -- -- -- -- -- -- -- 15 4 4 34 31.3 0.55 0.55 10 -- -- -- -- -- -- -- 20 4 4 4 4 -- -- -- -- 170 136 5.9 7.3 0.55 0.55 0.55 0.55
Min. -- 1 7.5 3.5 3.5 2.5 0.5 2.5 0.5 10 15 10 20 -- 1 1 32 29.4 0.45 0.45 -- 100 45 45 15 5 5 5 -- -- -- -- -- 5 7 2.5 0.5 160 128 -- 7.8 -- 0.45 -- 0.45
NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 10ns speed grade is available as a standard device. All other speed grades are available by special order. 3. To achieve 166MHz read and write port operation, the input and/or output bus must be configured to x24 or x18.
30
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS ASYNCHRONOUS TIMING
(Commercial: VCC = 2.5V 5%, TA = 0C to +70C;Industrial: VCC = 2.5V 5%, TA = -40C to +85C)
Commercial IDT72T6480L7-5 (x24 or x12 I/O width only)(3) Symbol fA tAa tCYC tCYCH tCYCL tFFa tEFa tPAFa tPAEa tRPE Parameter Asynchronous Clock Cycle Frequency Data Access Time Cycle Time Cycle High Time Cycle Low Time Rising Edge to FF Rising Edge to EF Rising Edge to PAF Rising Edge to PAE Read Pulse after EF HIGH Min. -- 0.6 10 4.5 4.5 -- -- -- -- 8 Max. 100 8 -- -- -- 8 8 8 8 -- Commercial IDT72T6480L7-5 Min. -- 0.6 12 5 5 -- -- -- -- 10 Max. 83 10 -- -- -- 10 10 10 10 -- Com'l & Ind'l(2) IDT72T6480L10 Min. -- 1 20 8 8 -- -- -- -- 14 Max. 50 12 -- -- -- 14 14 14 14 -- Unit MHz ns ns ns ns ns ns ns ns ns
NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 10ns speed grade is available as a standard device. All other speed grades are available by special order. 3. To achieve 166MHz read and write port operation, the input and/or output bus must be configured to x24 or x18.
31
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MRS REN
tRS tRSU tRSU tRH tRH tRH tRH tRSF
WEN
tRSU
SREN
tRSU
SWEN EF OR FF IR CK CK Q[47:0]
tRSU
FWFT Mode IDT Standard Mode If IDT mode is selected
tRSF
If FWFT mode is selected
tPL
If IDT mode is selected
tPL
If FWFT mode is selected
tPL
The clock may not be locked to the required operating frequency before tPL
tPL
The clock may not be locked to the required operating frequency before tPL If OE = HIGH If OE = LOW
FWFT
tRSU
Synchronous read port selected Asynchronous read port selected
ASYR
tRSU
Synchronous write port selected Asynchronous write port selected
ASYW
tRSU
3.3V I/O voltage selected 2.5V I/O voltage selected
IOSEL PAF
tRSF tRSF
PAE
tRSU
Depth Expansion in IDT Standard Mode Depth Expansion in FWFT Standard Mode
6358 drw14
IDEM
NOTE: 1. For other signals that are latched during master reset, refer to Master Reset and Device Configuration section.
Symbol tRS tRSU tRSH tPL tRSF
Parameter Reset Pulse Width Reset Setup Time Reset Hold Time Reset to PLL Lock Reset to Flag and Output
Min. 10 15 10 20 --
Max. -- -- -- -- 15
Unit ns ns ns s ns
Figure 6. Master Reset and Initialization
32 JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tRS PRS tRSU REN tRSU WEN tRSU SREN tRSU SWEN tRSF EF OR FF IR Q[47:0] tRSF PAF tRSF PAE
6358 drw15
tRH tRH tRH tRH
If IDT mode is selected
tRSF
If FWFT mode is selected
tRSF
If IDT mode is selected
tRSF
If FWFT mode is selected If OE = HIGH If OE = LOW
Symbol tRS tRSU tRSH tPL tRSF
Parameter Reset Pulse Width Reset Setup Time Reset Hold Time Reset to PLL Lock Reset to Flag and Output
Min. 10 15 10 20 --
Max. -- -- -- -- 15
Unit ns ns ns s ns
Figure 7. Partial Reset
33
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
WCLK tENS WEN tENS D[47:0] tENH
Word 1 Word 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tENH
Word 0
tSKEW1 RCLK REN tREFs EF tA Q[47:0]
Word 0 1 2
tENS
tENH
tREFs tA
Word 1
tA
Word 2
6358 drw16
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 8. Write First Word Cycles - IDT Standard Mode
WCLK tENS WEN tENS D[47:0] tENH
Word 1 Word 2
tENH
Word 0
tSKEW1 RCLK REN tREFs OR tA Q[47:0]
Word 0 1 2 3
tENS
tENH
tREFs tA
Word 1
tA
Word 2
6358 drw17
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH.
Figure 9. Write First Word Cycles - FWFT Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- 4 -- 4 Min. 5 5 1 5 -- Max. -- -- 5 -- 5 Min. 5 5 1 7 --
10ns Max. -- -- 6.5 -- 6.5 Unit ns ns ns ns ns JULY 29, 2004
Symbol tSENS tSENH tA tSKEW1 tREFs
Parameter Serial Enable Setup Serial Enable Hold Data Access Time Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR Read Clock to Synchronous EF/OR
Min. 5 5 1 4 -- 34
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
tCLKH tCLK tCLKL tENS
NO OPERATION NO OPERATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RCLK
tENS tENH
1
2
tENH
tENS
tENH
REN
tREF
tREF tA Last Word tOHZ tOLZ Last Word Word 0
tREF
EF
tA tA Word 1
Q[47:0] OE WCLK
tENS tOE tSKEW1
(1)
tENH
tENS
tENH
WEN D[47:0]
tDH tDS Word 0 tDS Word 1
6358 drw18
tDH
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 10. Empty Boundary - IDT Standard Mode
RCLK REN
1
2
3
tREFs OR tA Q[47:0]
Last Word - 3
tREFs
tA
Last Word - 2
tA
Last Word - 1 Last Word
tA
Word 0
tSKEW1 WCLK tENS WEN tDS D[47:0]
Word 0
tENH
tDH
6358 drw19 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH.
Figure 11. Empty Boundary - FWFT Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- -- -- -- -- -- 4 4 -- Min. 7.5 3.5 3.5 2.5 0.5 2.5 0.5 1 -- 5 Max. -- -- -- -- -- -- -- 5 5 --
10ns Min. 10 4.5 4.5 3.5 0.5 3.5 0.5 1 -- 7 Max. -- -- -- -- -- -- -- 6.5 6.5 -- Unit ns ns ns ns ns ns ns ns ns ns
Symbol tCLK tCLKH tCLKL tDS tDH tENS tENH tA tREFs tSKEW1
Parameter Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Read Clock to Synchronous EF/OR Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 35
Min. 6 2.7 2.7 2 0.5 2 0.5 1 -- 4
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
WCLK tENS WEN tDS D[47:0]
WD-1
1 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tENH
tSKEW1
tDH
WD
tWFFs FF
tWFFs
RCLK tENS REN tA Q[47:0]
Previous Word in Register Word 0
tA
Word 1
tA
Word 2
tA
Word 3
6358 drw20
NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle (plus tWFFs). If tSKEW1 is not met, then FF de-assertion may be delayed one extra WCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 12. Full Boundary - IDT Standard Mode
WCLK tENS WEN tDS D[47:0]
WD-1
1 2
tENH
tSKEW1
tDH
WD
tWFFs IR
tWFFs
RCLK tENS REN tA Q[47:0]
Word 0 Word 1
tA
Word 2
tA
Word 3
tA
Word 4
6358 drw21
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH.
Figure 13. Full Boundary - FWFT Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- -- -- 4 4 -- Min. 2.5 0.5 2.5 0.5 1 -- 5 Max. -- -- -- -- 5 5 --
10ns Min. 3.5 0.5 3.5 0.5 1 -- 7 Max. -- -- -- -- 6.5 6.5 -- Unit ns ns ns ns ns ns ns
Symbol tDS tDH tENS tENH tA tWFFs tSKEW1
Parameter Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Write Clock to Synchronous FF/IR Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 36
Min. 2 0.5 2 0.5 1 -- 4
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
RCLK REN tA Q[47:0]
Word 1 Word 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tA
Word 3
tA
Word 4 Word 4
tOHZ OE
tOE
6358 drw22
NOTE: 1. Settings: RCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 14. Output Enable
RCLK tENH REN tA Q[47:0]
Word 1 Word 2
tA
Word 3
tA
tRCSLZ
Word 4
tRCSHZ tA
Word 4
tENS RCS
tENS
6358 drw23
NOTE: 1. Settings: OE = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 15. Read Chip Select
WCLK tENS WEN tDS D[47:0]
Word 0
tDH
Word 1 Word 2
tWCSS WCS
NOTE: 1. Settings: BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
tWCSH
6358 drw24
Figure 16. Write Chip Select
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- -- -- 4 4 4 -- -- Min. 2.5 0.5 2.5 0.5 1 1 1 2.5 0.5 Max. -- -- -- -- 5 5 5 -- --
10ns Min. 3.5 0.5 3.5 0.5 1 1 1 3.5 0.5 Max. -- -- -- -- 6.5 6.5 6.5 -- -- Unit ns ns ns ns ns ns ns ns ns
Symbol tDS tDH tENS tENH tA tOHZ tOE tWCSS tWCSH
Parameter Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Output enable to High-Z Output Enable Valid WCS Setup Time WCS Hold Time 37
Min. 2 0.5 2 0.5 1 1 1 2 0.5
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
WCLK tENS tENH WEN tDS D[47:0] tDH
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Word 0
tSKEW1 RCLK REN tREFs EF tA Q[23:0]
Previous Word in Register D[47:24] 1 2
tENS
tENH
tREFs
tA
Word 0 D[23:0] Word 0 D[47:24]
6358 drw25
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1011, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 17. Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode
WCLK tENS tENH WEN tDS D[47:0] tDH
Word 0
tSKEW1 RCLK REN tREFS EF tA Q[11:0]
Previous Word in Register D[47:36] 1 2
tENS tREFS
tA
Word 0 D[11:0]
tA
Word 0 D[23:12]
tA
Word 0 D[35:24] Word 0 D[47:36]
6358 drw26
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1111, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 18. Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- -- -- 4 4 -- Min. 2.5 0.5 2.5 0.5 1 -- 5 Max. -- -- -- -- 5 5 --
10ns Min. 3.5 0.5 3.5 0.5 1 -- 7 Max. -- -- -- -- 6.5 6.5 -- Unit ns ns ns ns ns ns ns
Symbol tDS tDH tENS tENH tA tREFs tSKEW1
Parameter Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Read Clock to Synchronous EF/OR Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 38
Min. 2 0.5 2 0.5 1 -- 4
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
WCLK tENS WEN tDS D[23:0] tDH tDS tDH tENH
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Word 0 Q[23:0]
Word 0 Q[23:0]
tSKEW1 RCLK REN tREFS EF tA Q[47:0]
Previous Word in Register Word 0
6358 drw27
1
2
tENS
tENH tREFS
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1001, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 19. Bus-Matching Configuration - x24 In to x48 Out - IDT Standard Mode
WCLK tENS WEN tDS D[11:0] tDH
Word 0 Q[23:12] Word 0 Q[35:24] Word 0 Q[47:36]
tENH
Word 0 Q[11:0]
tSKEW1 RCLK
1 2 3
tENS REN tREFS EF
tENH tREFS tA
Q[47:0]
Previous Word in Register
Word 0
6358 drw28
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. 2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1101, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 20. Bus-Matching Configuration - x12 In to x48 Out - IDT Standard Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- -- -- 4 4 -- Min. 2.5 0.5 2.5 0.5 1 -- 5 Max. -- -- -- -- 5 5 --
10ns Min. 3.5 0.5 3.5 0.5 1 -- 7 Max. -- -- -- -- 6.5 6.5 -- Unit ns ns ns ns ns ns ns
Symbol tDS tDH tENS tENH tA tREFs tSKEW1
Parameter Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Data Access Time Read Clock to Synchronous EF/OR Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 39
Min. 2 0.5 2 0.5 1 -- 4
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
WCLK tENH WEN tDS D[47:0] PAE tDH
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Word n + 1
n words or less in Memory (2) n + 1 words or less in Memory
(2)
n + 1 words or more in Memory (2) n + 2 words or more in Memory (2)
tSKEW2 RCLK REN
1
tPAEs
2 1
tPAEs
2
tENS
tENH tA
Q[47:0]
Previous Word in Register
Word 0
6358 drw29
NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle (plus tPAEs). If tSKEW2 is not met, then PAE de-assertion may be delayed one extra RCLK cycle. 2. n = PAE offset, see Table 10 for information on setting PAE offset values. 3. Settings: OE = LOW, RCS = LOW, BM[3:0] = 1000, ASYR = HIGH, and ASYW = HIGH.
Figure 21. Synchronous PAE Flag - IDT Standard Mode and FWFT Mode
WCLK tDH WEN tDS D[47:0]
Word D - (m + 1) 1 2 1 2
tDH
Word D - m
tPAFs PAF
D - (m + 1) words or less in Memory D - m words or more in Memory
tPAFs
tSKEW2 RCLK tENS REN tA Q[47:0]
Previous Word in Register Word 0
6358 drw30
tENH
NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAF will go HIGH after one RCLK cycle (plus tPAFs). If tSKEW2 is not met, then PAF de-assertion may be delayed one extra RCLK cycle. 2. m = PAF offset, D = density of SFC, see Table 11 for information on setting PAF offset values. 3. Settings: OE = LOW, RCS = LOW, BM[3:0] = 1000, ASYR = HIGH, and ASYW = HIGH.
Figure 22. Synchronous PAF Flag - IDT Standard Mode and FWFT Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- -- 4 4 4 -- Min. 2.5 0.5 0.5 1 -- -- 7 Max. -- -- -- 5 5 5 --
10ns Min. 3.5 0.5 0.5 1 -- -- 10 Max. -- -- -- 6.5 6.5 6.5 -- Unit ns ns ns ns ns ns ns
Symbol tDS tDH tENH tA tPAFs tPAEs tSKEW2
Parameter Data Setup Time Data Hold Time Enable Hold Time Data Access Time WCLK to Synchronous PAF RCLK to Synchronous PAE Skew time between RCLK and WCLK for PAE/PAF 40
Min. 2 0.5 0.5 1 -- -- 5
JULY 29, 2004
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RD tAa Q[47:0]
Word D - (m - 2)
tAa
Word D - (m - 1) Word D - m
tAa
Word D - (m + 1)
tPAFa PAF
(D - m) words or more in Memory D - (m + 1) words or less in Memory
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NOTES: 1. m = PAF offset, see Table 10 for information on PAF offset values. D = density of SFC. 2. Settings: OE = LOW, RCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 3. Asynchronous read is available in IDT standard mode only.
Figure 23. Asynchronous Read and PAF Flag - IDT Standard Mode
WR tDS D[47:0] PAE
tDH
tDS
Word n
tDH
tDS
tDH
Word n - 1
Word n + 1
tPAEa
n words or less in Memory (1) n + 1 words or more in Memory (1)
NOTES: 1. n = PAE offset, see Table 11 for information on PAE offset values. 2. Settings: WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 3. Asynchronous read is available in IDT standard mode only.
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Figure 24. Asynchronous Write and PAE Flag - IDT Standard Mode
WR tDS D[47:0] PAF
tDH
tDS
tDH
tDS
tDH
Word D - (m + 2)
Word D - (m + 1)
Word D - m
tPAFa
D - (m + 1) words or less in Memory D - m words or more in Memory
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NOTES: 1. m = PAF offset, see Table 11 for information on PAF offset values. D = density of SFC. 2. Settings: WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 3. Asynchronous read is available in IDT standard mode only.
Figure 25. Asynchronous Write and PAF Flag - IDT Standard Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- 8 8 Min. 2.5 0.5 0.6 -- Max. -- -- 10 10
10ns Min. 3.5 0.5 1 -- Max. -- -- 12 14 Unit ns ns ns ns
Symbol tDS tDH tAa tPAFa
Parameter Data Setup Time Data Hold Time Data Access Time Rising Edge to PAF 41
Min. 2 0.5 0.6 --
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
tCYC tCYCH tCYCL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
WR
tDS
tDH
tDS
tDH
D[47:0] RD
Word 0
Word 1
tRPE tAa tAa
Word 0 Word 1
Q[47:0] EF
Previous word in register
tEFa
tEFa
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NOTES: 1. Settings: OE = LOW, RCS = LOW, WCS = LOW, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 2. Asynchronous read is available in IDT standard mode only.
Figure 26. Asynchronous Empty Boundary - IDT Standard Mode
WR
tDS tDH
D[47:0] RD
WD
tAa
Q[47:0]
tFFa
Previous word in register
Word 0
tFFa
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FF
NOTES: 1. Settings: OE = LOW, RCS = LOW, WCS = LOW, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 2. Asynchronous read is available in IDT standard mode only.
Figure 27. Asynchronous Full Boundary - IDT Standard Mode
RD
tAa tAa
Word n - 2 Word n - 1
tAa
Word n
Q[47:0] PAE
Word n - 3
tPAEa
n words or less in Memory (1) n words or more in Memory (1)
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NOTES: 1. n = PAE offset, see Table 11 for information on PAE offset values. 2. Asynchronous read is available in IDT standard mode only.
Figure 28. Asynchronous Read and PAE Flag - IDT Standard Mode
7-5ns
(x24 or x12 I/O only)
7-5ns Max. 8 -- -- -- -- -- 8 8 8 -- Min. 0.6 12 5 5 0.5 2.5 -- -- -- 10 Max. 10 -- -- -- -- -- 10 10 10 --
10ns Min. 1 20 8 8 0.5 3.5 -- -- -- 14 Max. 12 -- -- -- -- -- 14 14 14 -- Unit ns ns ns ns ns ns ns ns ns ns
Symbol tAa tCYC tCYCH tCYCL tDH tDS tEFa tFFa tPAEa tRPE
Parameter Data Access Time Cycle Time Cycle HIGH Time Cycle LOW Time Data Hold Time Data Setup Time Rising Edge to EF Rising Edge to FF Rising Edge to PAE Read Pulse after EF HIGH 42
Min. 0.6 10 4.5 4.5 0.5 2 -- -- -- 8
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SCLK
tSENS
tSENH tENH
SWEN
tDS tDH
BIT X EMPTY OFFSET BIT 0 FULL OFFSET BIT X
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SI
BIT 0
NOTES: 1. Settings: JSEL = LOW. 2. x is the required number of bits to program the PAE and PAF offset registers. See Table 12 for the numbers based on the values external configurations.
Figure 29. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tSCKH
tSCLK tSCKL
SCLK
tSENS tSENH
SREN
tASO
SDO
BIT 0 (LSB) EMPTY OFFSET
BIT X
BIT 0 FULL OFFSET
BIT X (MSB)
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NOTES: 1. Settings: JSEL = LOW. 2. x is the required number of bits to program the PAE and PAF offset registers. See Table 12 for the numbers based on the values external configurations.
Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes)
7-5ns
(x24 or x12 I/O only)
7-5ns Max. -- -- 20 -- -- -- -- -- Min. 0.5 2.5 -- 5 5 10 45 45 Max. -- -- 20 -- -- -- -- --
10ns Min. 0.5 3.5 -- 5 5 10 45 45 Max. -- -- 20 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns
Symbol tDH tDS tASO tSENS tSENH tSCLK tSCLKH tSCLKL
Parameter Data Hold Time Data Setup Time Serial Output Data Access Time Serial Enable Setup Serial Enable Hold Serial Clock Cycle Serial Clock HIGH Serial Clock LOW
Min. 0.5 2 -- 5 5 10 45 45
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tTCK t4 t1
TCK
t2
t3
TDI/ TMS
tDS
TDO
tDH
TDO
tDO
Notes to diagram: t1 = tTCKLOW t2 = tTCKHIGH t3 = tTCKFALL t4 = tTCKRISE
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Figure 31. Standard JTAG Timing
SYSTEM INTERFACE PARAMETERS
IDT72T6480 Parameter Data Output Data Output Hold Data Input Symbol tDO(1) tDOH(1) tDS tDH trise=3ns tfall=3ns Test Conditions Min. 0
10 10
(vcc = 2.5V 5%; Tambient (Industrial) = 0C to +85C)
Parameter Symbol
JTAG AC ELECTRICAL CHARACTERISTICS
Test Conditions Min. 100 40 40 Max. Units 5(1) 5(1) ns ns ns ns ns
Max. Units 20 -
JTAG Clock Input Period tTCK JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time
NOTE: 1. Guaranteed by design.
ns ns ns
tTCKHIGH tTCKLOW tTCKRISE tTCKFALL
NOTE: 1. 50pf loading on external output signals.
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
JTAG TIMING SPECIFICATIONS (IEEE 1149.1 COMPLIANT)
The JTAG test port in this device is fully compliant with the IEEE Standard Test Access Port (IEEE 1149.1) specifications. Four additional pins (TDI, TDO, TMS and TCK) are provided to support the JTAG boundary scan interface. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices.
* * * * * *
The Standard JTAG interface consists of seven basic elements: Test Access Port (TAP) TAP controller Instruction Register (IR) Data Register Port (DR) Bypass Register (BYR) ID Code Register
The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). The Figure below shows the standard Boundary-Scan Architecture
All inputs Eg: Dins, Clks (BSDL file describes the chain order)
In Pad
Incell Core Logic
Outcell
Out Pad All outputs
In Pad
Incell
Outcell
Out Pad
TDI
ID Bypass
TMS TCK
Instruction Register TAP Instruction Select Enable
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TDO
Figure 32. JTAG Architecture
TEST ACCESS PORT (TAP) The TAP interface is a general-purpose port that provides access to the internal JTAG state machine. It consists of three input ports (TCLK, TMS, TDI) and one output port (TDO).
THE TAP CONTROLLER The TAP controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and updating of data passed through the TDI serial input.
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
Test-Logic Reset 0 1 1 1 SelectIR-Scan 1 0 Capture-IR 0 Shift-IR 1 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0
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Input is TMS
0
Run-Test/ Idle
SelectDR-Scan 0 1 Capture-DR 00 Shift-DR 1 Exit1-DR 00 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
0
1
0
NOTES: 1. Five consecutive 1's at TMS will reset the TAP. 2. TAP controller resets automatically upon power-up.
Figure 33. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram All state transitions within the TAP controller occur at the rising edge of the TCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. Test-Logic-Reset All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP controller state machine is designed in such a way that, no matter what the initial state of the controller is, the Test-Logic-Reset state can be entered by holding TMS at high and pulsing TCK five times. Run-Test-Idle In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it will be executed when the controller enters this state. The test logic in the IC is idle otherwise. Select-DR-Scan This is a controller state where the decision to enter the Data Path or the Select-IR-Scan state is made. Select-IR-Scan This is a controller state where the decision to enter the Instruction Path is made. The Controller can return to the Test-Logic-Reset state other wise. Capture-IR In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of fixed values on the rising edge of TCK. The last two significant bits are always required to be "01".
46
Shift-IR In this controller state, the instruction register gets connected between TDI and TDO, and the captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI pin is also shifted in to the instruction register. TDO changes on the falling edge of TCK. Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made. Pause-IR This state is provided in order to allow the shifting of instruction register to be temporarily halted. Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made. Update-IR In this controller state, the instruction in the instruction register scan chain is latched in to the register of the Instruction Register on every falling edge of TCK. This instruction also becomes the current instruction once it is latched. Capture-DR In this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of TCK. Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path.
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
THE INSTRUCTION REGISTER The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR. TEST DATA REGISTER The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register. These registers are connected in parallel between a common serial input and a common serial data output. The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). TEST BYPASS REGISTER The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in the serial path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state. The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction. THE BOUNDARY-SCAN REGISTER The boundary-scan register (BSR) contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins, and/ or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. THE DEVICE IDENTIFICATION REGISTER The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the device to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72T6480, the Part Number field contains the following values:
JTAG INSTRUCTION REGISTER The Instruction register allows an instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: * Select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip operation and the selected data register. * Define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode 16 different possible instructions. Instructions are decoded as follows. Hex Value 0000 0001 0002 0003 0008 000F Instruction EXTEST SAMPLE/PRELOAD IDCODE HIGH-IMPEDANCE CLAMP BYPASS Private Function Test external pins Select boundary scan register Selects chip identification register Puts all outputs in high-impedance state Fix the output chains to scan chain values Select bypass register Several combinations are private (for IDT internal use). Do not use codes other than those identified above.
JTAG INSTRUCTION REGISTER DECODING The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). EXTEST The required EXTEST instruction places the device into an external boundary-test mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. As such, the EXTEST instruction is the workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. SAMPLE/PRELOAD The required SAMPLE/PRELOAD instruction allows the device to remain in a normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the device. This instruction is also used to preload test data into the boundary-scan register before loading an EXTEST instruction.
IDCODE The optional IDCODE instruction allows the device to remain in its functional mode and selects the optional device identification register to be connected between TDI and TDO. The device identification register is a 32-bit shift register 31(MSB) 28 27 12 11 1 0(LSB) containing information regarding the device manufacturer, device type, and version code. Accessing the device identification register does not interfere with Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) the operation of the device. Also, access to the device identification register 0000 0033 (hex) 1 should be immediately available, via a TAP data-scan operation, after powerIDT72T6480 JTAG Device Identification Register up of the device or by otherwise moving to the Test-Logic-Reset state.
Device IDT72T6480
Part# Field 0438 (hex)
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLAMP The optional CLAMP instruction sets the outputs of an device to logic levels determined by the contents of the boundary-scan register and selects the onebit bypass register to be connected between TDI and TDO. Before loading this instruction, the contents of the boundary-scan register can be preset with the SAMPLE/PRELOAD instruction. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the outputs. HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types) of an device to a disabled (high-impedance) state
and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the device outputs. BYPASS The required BYPASS instruction allows the device to remain in a normal functional mode and selects the one-bit bypass register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the device.
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DEPTH EXPANSION CONFIGURATION
The sequential flow-control (SFC) device can be connected with multiple SFCs in depth expansion to provide additional storage density that's greater than 1Gb. In depth expansion mode, two or mode devices are connected through a common transfer interface, as shown in Figure 34. The transfer clock can be a separate free-running clock or driven from the same system write or read clock. In depth expansion configuration, the first word written to an empty configuration will pass from the first SFC to the next until it appears on the second (or last) SFC in the chain. If no reads are performed, data will begin accumulating in the second SFC until it is full. Once the second SFC is full it will disable the REN to the first SFC. At this point data will begin accumulating in the first SFC. Once both devices are full, the entire configuration is full and the full flag indicator will go LOW. For an empty configuration, the amount of time it takes for the empty flag of the second (or last) SFC in the chain to go LOW (i.e. valid data available to be
read out of the device) after a word has been written into the first FIFO is the sum of the delays for each individual SFC: (N - 1) x (4 x transfer clock) + 3 x RCLK Where N is the number of SFCs in the chain and RCLK is the RCLK period in ns. This latency is only noticeable for the first word written to an empty configuration. There will be no delay evident for subsequent words written into the chain. In the full configuration, the amount of time it takes for the FF of the first SFC to go from LOW to HIGH after reading one word from the chain is the sum of the delays for each individual SFC: (N - 1) x (3 x transfer clock) + 2 x WCLK Depth expansion is available in both IDT Standard mode and First Word Fall Through (FWFT) mode. If IDT Standard mode is selected, the IDEM signal needs to be HIGH. If FWFT mode is selected, the IDEM signal needs to be LOW.
VCC GND Transfer Clock Write Clock Write Enable Full Flag Data Inputs Dn IDEM Qn Dn IDEM Qn FWFT WCLK WEN FF SFC #1 RCLK OR REN WCLK WEN IR SFC #2 FWFT RCLK EF REN Read Clock Empty Flag Read Enable Data Outputs
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VCC
VCC
Figure 34. Depth Expansion Configuration in IDT Standard Mode
VCC Transfer Clock Write Clock Write Enable Input Ready Flag Data Inputs Dn IDEM Qn Dn IDEM Qn FWFT WCLK WEN IR SFC #1 RCLK OR REN WCLK WEN IR SFC #2 FWFT RCLK OR REN Read Clock Output Ready Flag Read Enable Data Outputs
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GND
GND
Figure 35. Depth Expansion Configuration in FWFT Mode
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IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
WIDTH EXPANSION CONFIGURATION
The sequential flow-control (SFC) device can be connected with another SFCs in width expansion to support bus-widths greater than 36-bits. This configuration connects the input and output bus of two devices together to create a wider bus. The read and write clocks for each device are driven with a clock driver. The empty and full flags of both devices are connected to a logic gate (AND/OR) depending on whether IDT Standard mode or FWFT mode is selected. Because of the variation in skew between the read clock and write
clock, it is possible for EF/FF deassertion and IR/OR assertion to vary from one cycle between the devices. The logic gate connected to the status flags will create a composite flag that will update the status of both SFC devices to represent a more accurate status of the configuration. To minimize the skew between the two write and read clocks, a clock driver (IDT5T905 recommended) is used to drive the input clocks for both SFC devices. Figure 36 illustrates the width expansion configuration.
Clock Driver IDT5T905
Write Clock Write Enable Full Flag/Input Ready Data Inputs
SFC WCLK WEN FF/IR Dn RCLK REN EF/OR
Read Clock Read Enable Empty Flag/Output Ready Data Outputs
Clock Driver IDT5T905
Gate
(1)
64
36
Qn
36
64
Gate
(1)
Clock Driver IDT5T905
Write Clock WCLK WEN Full Flag/Input Ready 36 FF/IR Dn
SFC RCLK REN EF/OR Qn 36
Read Clock
Clock Driver IDT5T905
Empty Flag/Output Ready
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NOTES: 1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode. 2. Do not connect any output signals directly together.
Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode
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ORDERING INFORMATION
IDT XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK I(1) BB Commercial (0C to +70C) Industrial (-40C to +85C) Plastic Ball Grid Array (PBGA, BB324)
7-5 10
Commercial and Industrial
Clock Cycle Time (tCLK) Speed in Nanoseconds
L 72T6480
Low Power
2.5V Sequential Flow-Control Device configurable to x12, x24, or x48
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DATASHEET DOCUMENT HISTORY
07/29/2004 pgs. 1, 4, 7-11, 13-25, 27-29, 31-43, 47, 49, and 51. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
51
for Tech Support: 408-330-1533 email: Flow-Controlhelp@idt.com

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